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Delay Analysis on-chip VLSI Interconnect using Gamma Distribution Function
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 1 - Number 3 |
| Year of Publication: 2010 |
| Authors: R. Kar, V. Maheshwari, Ashis K. mal, A.K.Bhattacharjee |
10.5120/81-176
|
R. Kar, V. Maheshwari, Ashis K. mal, A.K.Bhattacharjee . Delay Analysis on-chip VLSI Interconnect using Gamma Distribution Function. International Journal of Computer Applications. 1, 3 ( February 2010), 65-68. DOI=10.5120/81-176
Abstract
Moments of the impulse response are widely used for interconnect delay analysis, from the explicit Elmore delay (the first moment of the impulse response) expression, to moment matching methods which creates reduced order trans-impedance and transfer function approximations. However, the Elmore delay is fast becoming ineffective for deep submicron technologies, and reduced order transfer function delays are impractical for use as early-phase design metrics or as design optimization cost functions. This paper describes an approach for fitting moments of the impulse response to probability density functions so that delay can be estimated accurately at an early physical design stage. For RC trees it is demonstrated that the incomplete gamma function provides a provably stable approximation. The accuracy of our model is justified with the results compared with that of SPICE simulations.
References
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