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Implementation of Low Power Scalable Encryption Algorithm

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International Journal of Computer Applications
© 2010 by IJCA Journal
Number 1 - Article 3
Year of Publication: 2010
Authors:
K.J. Jegadish Kumar
S. Salivahanan
K. Chenna Kesava Reddy
10.5120/1548-2060

Jegadish K J Kumar, S Salivahanan and Chenna Kesava K Reddy. Article:Implementation of Low Power Scalable Encryption Algorithm. International Journal of Computer Applications 11(1):14–18, December 2010. Published By Foundation of Computer Science. BibTeX

@article{key:article,
	author = {K.J. Jegadish Kumar and S. Salivahanan and K. Chenna Kesava Reddy},
	title = {Article:Implementation of Low Power Scalable Encryption Algorithm},
	journal = {International Journal of Computer Applications},
	year = {2010},
	volume = {11},
	number = {1},
	pages = {14--18},
	month = {December},
	note = {Published By Foundation of Computer Science}
}

Abstract

Scalable Encryption algorithm (SEA) is a symmetric block cipher, especially designed for resources constrain systems. SEA proposes low cost encryption routines (i.e. small code size, memory and power), targeted for processors with a limited instruction set. SEA is parametric with text, key and processor size, and allows efficient combination of encryption/decryption and key derivation. SEA was initially designed for software implementations in controllers, smart cards, or processors and small embedded applications. In this paper, we investigate the performance of SEA in a Field programmable gate array (FPGA) device. For this purpose, an iterative loop design of the block cipher is implemented on FPGA. Beyond its low cost performances, the proposed architecture is fully flexible with any parameters and takes advantage of generic VHDL coding. Our efficient modular adders implementation achieves lower area, power consumption and considerably higher throughputs on the target platform VIRTEX-4, xc4vl25 and SPARTAN-3, xc3s1400.

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