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A Scheduling Algorithm for Asymmetric Processor Architecture

International Journal of Computer Applications
© 2010 by IJCA Journal
Number 11 - Article 8
Year of Publication: 2010

S.Subha. Article:A Scheduling Algorithm for Asymmetric Processor Architecture. International Journal of Computer Applications 11(11):44–48, December 2010. Published By Foundation of Computer Science. BibTeX

	author = {S.Subha},
	title = {Article:A Scheduling Algorithm for Asymmetric Processor Architecture},
	journal = {International Journal of Computer Applications},
	year = {2010},
	volume = {11},
	number = {11},
	pages = {44--48},
	month = {December},
	note = {Published By Foundation of Computer Science}


Chip multiprocessors are used widely today. The cores in a chip can be homogeneous or heterogeneous. This paper proposes a scheduling algorithm for heterogeneous multiprocessors wotj, multiple functional units of varying speed in each processor. Instructions that can be scheduled in parallel are considered. An optimization function is developed to allocate the processes to the processors that minimize the overall execution time. The proposed model is simulated for a chosen example and verified to give 46% improvement in performance.


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