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A Scheduling Algorithm for Asymmetric Processor Architecture
International Journal of Computer Applications
© 2010 by IJCA Journal
Number 11 - Article 8
Year of Publication: 2010
|
10.5120/1623-2182 |
S.Subha. Article:A Scheduling Algorithm for Asymmetric Processor Architecture. International Journal of Computer Applications 11(11):44–48, December 2010. Published By Foundation of Computer Science. BibTeX
@article{key:article,
author = {S.Subha},
title = {Article:A Scheduling Algorithm for Asymmetric Processor Architecture},
journal = {International Journal of Computer Applications},
year = {2010},
volume = {11},
number = {11},
pages = {44--48},
month = {December},
note = {Published By Foundation of Computer Science}
}
Abstract
Chip multiprocessors are used widely today. The cores in a chip can be homogeneous or heterogeneous. This paper proposes a scheduling algorithm for heterogeneous multiprocessors wotj, multiple functional units of varying speed in each processor. Instructions that can be scheduled in parallel are considered. An optimization function is developed to allocate the processes to the processors that minimize the overall execution time. The proposed model is simulated for a chosen example and verified to give 46% improvement in performance.
Reference
- Ioannis Chatzigiannakis, Georgios Giannoulis, Paul Spirakis, Scheduling Tasks with Dependencies on Asymmetric Multiprocessors, PODC, ‘08
- Nagesh B. Lakshminarayana, Jaekyu Lee, Hyesoon Kim, Age based scheduling for asymmetric multiprocessors, Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis, 2009
- Qiong Cai , José González , Ryan Rakvic , Grigorios Magklis , Pedro Chaparro , Antonio González, Meeting points: using thread criticality to adapt multicore hardware to parallel regions, Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008
- Saisanthosh Balakrishnan , Ravi Rajwar , Mike Upton , Konrad Lai, The Impact of Performance Asymmetry in Emerging Multicore Architectures, Proceedings of the 32nd annual international symposium on Computer Architecture, 2005, pp. 506-517
- S. Subha: An Algorithm for Parallel Execution of Loops in Chip Multiprocessor Caches, ARTCom 2009: 85-89
- S. Subha: A Scheduling Algorithm for Network on Chip, Advances in Computing, Control, and Telecommunication Technologies, International Conference on, pp.289-291