Call for Paper - August 2020 Edition
IJCA solicits original research papers for the August 2020 Edition. Last date of manuscript submission is July 20, 2020. Read More

Power Optimized ALU for Efficient Datapath

International Journal of Computer Applications
© 2010 by IJCA Journal
Number 11 - Article 7
Year of Publication: 2010
K.Lal Kishore

M.Kamaraju, K.Lal Kishore and A.V.N.Tilak. Article:Power Optimized ALU for Efficient Datapath. International Journal of Computer Applications 11(11):39–43, December 2010. Published By Foundation of Computer Science. BibTeX

	author = {M.Kamaraju and K.Lal Kishore and A.V.N.Tilak},
	title = {Article:Power Optimized ALU for Efficient Datapath},
	journal = {International Journal of Computer Applications},
	year = {2010},
	volume = {11},
	number = {11},
	pages = {39--43},
	month = {December},
	note = {Published By Foundation of Computer Science}


With the scaling of technology and the need for high performance and more functionality, power dissipation becomes a major bottleneck for microprocessor systems design. Also clock power can be significant in high performance systems. In this paper, a low power ALU for efficient datapath is proposed. In ALU, based on the observation, that while one functional unit is working other functional units remain idle, but they are connected to clock and all units dissipating significant amount of power. By using clock gating technique, a significant amount of power saving can be achieved at high frequency operations. Functionality of proposed ALU implemented on FPGA is tested using Xilinx tool. Power analysis is carried out using Xilinx’s Xpower analysis tool. It is found that designed ALU is dissipating a power of 24mw when it is operated at a clock frequency of 15MHz and supply voltage of 2.4V under load current of 4.8mA


  • Ahmad Zmily, Christos Kozyrakis, “A Low Power Front-End for Embedded Processors Using a Block-Aware Instruction Set”, Proc. of the Automation Science & Engineering (CASE 07), 2007, pp. 267-276.
  • Bill Moyer, “Low Power Design for Embedded Processor”, Proc. of IEEE, Vol.89, No.11, 2001, pp.1576-1586.
  • Castro J, Parra P, Acosta A.J., “Optimization of Clock-gating Structures for Low-leakage High-performance Applications,” Proc. of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, pp. 3220 – 3223.
  • Kamaraju M, Lal Kishore K, Tilak A.V.N, “Power Optimized Programmable Embedded Controller”, International Journal of Computer Networks & Communications (IJCNC), Vol.2, No.4, 2010, pp 97 – 107.
  • Kamaraju M, Lal Kishore K, Tilak A.V.N, “Implementation of Low Power Datapath and Control Units of 8- bit Processor,” International Journal on Recent Trends in Engineering & Technolgy , 2010 , in press.
  • Michael K.Gowan, Larry L.Biro, Daniel B.Jackson, “Power Considerations in the Design of the Alpha 21264 Microprocessor”, Proc. of the 35th Design Automation Conference (DAC'98), 1998, pp. 726- 731.
  • Monica Donno, Enrico Macii, Luca Mazzoni, “Power-Aware Clock Tree Planning”, ISPD’04, 2004, pp. 138-147.
  • Pietro Babighian, Luca Benini, Enrico Macii, “A Scalable Algorithm for RTL Insertion of Gated Clocks Based on ODCs Computation”, IEEE Trans. Computer-Aided Design, Vol. 24, No. 1, 2005, pp.29-42.
  • Qi Wang, Sumit Roy, “RTL Power Optimization with Gate-level Accuracy,” Proc. of the International Conference on Computer Aided Design (ICCAD’03), 2003, pp. 39-45.
  • Richa Srivastava, S.A .Imam, Sujata Pandey, “Low Power Design Techniques for high performance Digital Integrated Circuits,” MASAUM Journal of Reviews and Surveys, Vol. 1, No.1, 2009, pp.81-90.
  • Rolf Hakenes, Yiannos Manoli, “A Novel Low – Power Microprocessor Architecture” Proc. of the International Conference on Computer Design: VLSI in Computers & Processors, 2000, pp.141- 146.
  • Saeid Moslehpour, Srikrishna Karatalapu, “VLSI and SPICE Modeling of ALU,” Proc. of the 2008 IAJC-IJME International Conference, 2008, pp. 401-415.
  • Steve Haga, Natasha Reeves, Rajeev Barua, Diana Marculescu, “Dynamic Functional Unit Assignment for Low Power”, Proc. of the Design, Automation and Test in Europe Conference and Exhibition (DATE’03), 2003, pp. 1-6.
  • Sulaiman, D.R., “Using Clock Gating Technique for Energy Reduction in Portable Computers”, Proc. of International Conference on Computer and Communication Engineering, ICCCE 2008, pp.839 – 842.
  • Swaroop Ghosh and Kaushik Roy, “Exploring High-Speed Low-Power Hybrid Arithmetic Units at Scaled Supply and Adaptive Clock-Stretching,” Proc. of the 2008 Asia and South Pacific Design Automation Conference, pp.635 – 640.