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Power Optimized ALU for Efficient Datapath

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International Journal of Computer Applications
© 2010 by IJCA Journal
Number 11 - Article 7
Year of Publication: 2010
Authors:
M.Kamaraju
K.Lal Kishore
A.V.N.Tilak
10.5120/1624-2185

M.Kamaraju, K.Lal Kishore and A.V.N.Tilak. Article:Power Optimized ALU for Efficient Datapath. International Journal of Computer Applications 11(11):39–43, December 2010. Published By Foundation of Computer Science. BibTeX

@article{key:article,
	author = {M.Kamaraju and K.Lal Kishore and A.V.N.Tilak},
	title = {Article:Power Optimized ALU for Efficient Datapath},
	journal = {International Journal of Computer Applications},
	year = {2010},
	volume = {11},
	number = {11},
	pages = {39--43},
	month = {December},
	note = {Published By Foundation of Computer Science}
}

Abstract

With the scaling of technology and the need for high performance and more functionality, power dissipation becomes a major bottleneck for microprocessor systems design. Also clock power can be significant in high performance systems. In this paper, a low power ALU for efficient datapath is proposed. In ALU, based on the observation, that while one functional unit is working other functional units remain idle, but they are connected to clock and all units dissipating significant amount of power. By using clock gating technique, a significant amount of power saving can be achieved at high frequency operations. Functionality of proposed ALU implemented on FPGA is tested using Xilinx tool. Power analysis is carried out using Xilinx’s Xpower analysis tool. It is found that designed ALU is dissipating a power of 24mw when it is operated at a clock frequency of 15MHz and supply voltage of 2.4V under load current of 4.8mA

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