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Reconfigurable FFT System on Chip (SOC)

International Journal of Computer Applications
© 2010 by IJCA Journal
Number 5 - Article 8
Year of Publication: 2010
G. Venkataramana Sagar
Dr. K. Srinivasa Rao

Venkataramana G Sagar and Dr. Srinivasa K Rao. Article:Reconfigurable FFT System on Chip (SOC). International Journal of Computer Applications 11(5):35–38, December 2010. Published By Foundation of Computer Science. BibTeX

	author = {G. Venkataramana Sagar and Dr. K. Srinivasa Rao},
	title = {Article:Reconfigurable FFT System on Chip (SOC)},
	journal = {International Journal of Computer Applications},
	year = {2010},
	volume = {11},
	number = {5},
	pages = {35--38},
	month = {December},
	note = {Published By Foundation of Computer Science}


With onset of paradigms of System On Chip (SOC) to design a module for real time applications or voice codec’s, The SOC’s have different requirements for operands precision we propose a reusable FFT [2] using reconfigurable multiplier [6]. How ever, the FFT perform either combining N and N/2 bit multiplications in the same N bit tree multiplier. The key challenges in designing a reusable FFT are to limit the impact of flexibility on power operations that are needed for FFT butterfly to perform better than a conventional, dedicated FFT butterfly.


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