Call for Paper - August 2022 Edition
IJCA solicits original research papers for the August 2022 Edition. Last date of manuscript submission is July 20, 2022. Read More

Cache Controller for 4-way Set-Associative Cache Memory

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2015
Praveena Chauan, Gagandeep Singh, Gurmohan Singh

Praveena Chauan, Gagandeep Singh and Gurmohan Singh. Article: Cache Controller for 4-way Set-Associative Cache Memory. International Journal of Computer Applications 129(1):1-8, November 2015. Published by Foundation of Computer Science (FCS), NY, USA. BibTeX

	author = {Praveena Chauan and Gagandeep Singh and Gurmohan Singh},
	title = {Article: Cache Controller for 4-way Set-Associative Cache Memory},
	journal = {International Journal of Computer Applications},
	year = {2015},
	volume = {129},
	number = {1},
	pages = {1-8},
	month = {November},
	note = {Published by Foundation of Computer Science (FCS), NY, USA}


This paper presents design of a cache controller for 4-way set associative cache memory and analyzing the performance in terms of cache hit verses miss rates. An FSM based cache controller has been designed for a 4-way set-associative cache memory of 1K byte with block size of 16 bytes. Main memory of 4K byte has been considered. The synthesis has been performed using Xilinx Synthesis Tool (XST) with Virtex-6 FPGA device XC6VLX240T. ISim simulator is used for functional verification of the designed code.The maximum output required time i.e. hold-time after clock is 0.777ns and minimum input time before clock arrival i.e. setup-time for designed module is 1.66ns. The maximum clock frequency is 257.202MHz.The design has also been synthesized in Cadence RTL Compiler tool. Finally, ASIC implementation of the designed cache controller has been done in Cadence Encounter Digital Implementation tool and the GDSII file has been generated.The designed cache controller consumes 5.53mW of total power.


  1. John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, 4th ed. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 2006.
  2. Maurice V. Wilkes, “The memory gap and the future of high performance memories”, SIGARCH Comput. Archit. News, 29(1), 2–7 March, 2001.
  3. A. J. Smith, “Cache memories”, ACM Computing Surveys, vol. 14, no. 3, pp. 473-530, September 1982.
  4. Bani R.R, Mohanty, S.P, Kougianos E, and Thakral G, “Design of a Reconfigurable Embedded Data Cache”, inProc. Int. Symp. Electronic System Design, pp.163-168, December 2010.
  5. Chuanjun Zhang, Vahid F, and Lysecky R, “A self-tuning cache architecture for embedded systems”, inProc. Europe Conf. and Exhibition on Design, Automation and Test, vol.1, pp.142,147, 16-20 February 2004.
  6. Frank Vahid and Tony Givargis, Embedded System Design: A Unified Hardware / Software Approach. John Wiley & Sons, 2006.
  7. Chenxu Wang, Jiamin Zheng, and Mingyan Yu, “Cache Performance Research for Embedded Processors” inProc. SciVerse Science Direct Int. Conf. Solid State Devices and Materials Science, pp.1322-1328, March 2012.
  8. Hassan S.L.M, Johari M.N, Saparon A, Halim I.S.A, and Ab Rahim A.A, “Multi-sized Output Cache Controllers”, in Proc. Int. Conf. Technology, Informatics, Management, Engineering & Environment (TIME-E 2013), Bandung, Indonesia, pp.186-191, June 2013.
  9. Chuanjun Zhang, “An efficient direct mapped instruction cache for application-specific embedded systems”, inProc. Third IEEE/ACM/IFIP Int. Conf. Hardware/Software Co design and System Synthesis, pp.45-50, September 2005.
  10. Crisu D, “An architectural survey and modelling of data cache memories in Verilog HDL”, inProc. Int. Semiconductor Conf. CAS '99, vol.1, pp.139, 142, 1999.
  11. Chuanjun Zhang, Vahid F, and Najjar W, “A highly configurable cache architecture for embedded systems”, inProc. 30th Annual Int. Symp. Computer Architecture, pp.136-146, June 2003.
  12. Bhure V.S and Padole D, “Design of Cache Controller for Multi-core Systems using Multilevel Scheduling Method”, inProc. Fifth Int. Conf. Emerging Trends in Engineering and Technology (ICETET), pp.167-173, November 2012.
  13. Sparsh Mittal, “A survey of architectural techniques for improving cache power efficiency”, Sustainable Computing: Informatics and Systemsvol.4, Issue 1, pp. 33-43,March 2014.
  14. Givargis T, “Improved indexing for cache miss reduction in embedded systems”, inProc. Conf. Design Automation, pp.875,880, 2-6 June 2003.
  15. Malik A, Moyer B, and Cermak D, “A low power unified cache architecture providing power and performance flexibility”, inProc. Int. Symp. Low Power Electronics and Design (ISLPED), pp. 241,243, 2000.
  16. Agarwal A and Pudar S.D, “Column-associative Caches: A Technique For Reducing The Miss Rate Of Direct-mapped Caches”, inProc. 20th Annual Int. Symp. Computer Architecture, pp.179,190, 16-19 May 1993.
  17. James K.Peckol and Embedded Systems: A Contemporary Design Tool. John Wiley & Sons, 2008.
  18. Olukotun K, Mudge T.N, and Brown R.B, “Multilevel optimization of pipelined caches”, IEEE Trans. Computers, vol.46, no.10, pp.1093-1102, Oct 1997.
  19. Dash A and Petrov P, “Energy-Efficient Cache Coherence for Embedded Multi-Processor Systems through Application-Driven Snoop Filtering”, 9th EUROMICRO Conf. Digital System Design: Architectures, Methods and Tools, pp.79,82, 2006.
  20. Balwant Raj, Anita Suman, Gurmohan Singh, “Analysis of Power Dissipation in DRAM Cells Design for Nanoscale Memories”, International Journal of Information Technology & Knowledge Management, July-December 2009, Volume-2,No. 2,pp. 371-374.
  21. Karishma Bajaj, Manjit Kaur, Gurmohan Singh,” Design and Analysis of Hybrid CMOS SRAM Sense Amplifier, International Journal of Electronics and Computer Science Engineering, Volume-1, Number-2, pp. 718-726, 2012.


Cache Memory, Main Memory, Set-Associative Cache Design, Cache Controller.