The week's pick
Reseach Article
Error Detection in 2-bit & 4-bit Multiplier using Parity Predictor Circuit in QCA
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 131 - Number 15 |
| Year of Publication: 2015 |
| Authors: Ankita Laad, Namit Gupta, Nilesh Patidar |
10.5120/ijca2015907414
|
Ankita Laad, Namit Gupta, Nilesh Patidar . Error Detection in 2-bit & 4-bit Multiplier using Parity Predictor Circuit in QCA. International Journal of Computer Applications. 131, 15 ( December 2015), 27-31. DOI=10.5120/ijca2015907414
Abstract
Error detection is the detection of errors caused by noise or other impairments during the transmission of signal from transmitter to receiver. Logic design errors may occur during simulation and synthesis due to increase in the complexity of CMOS and VLSI circuits. Error detection method can be either systematic or non-systematic. In systematic method, the transmitter sends the original data unit, and a fixed number of check bits or Parity data is been attached to it, which are derived from the same input data unit. In this work, we describe a method of error detection in 4-bit multiplier with parity predictor circuit in QCA tool. 4-bit multiplier is used as a logic in which we detect error according to its input data. The outputs of logic used and the parity predictor are then compared using comparator. If the values do not match, error has occurred. The technique we used is Concurrent error detection using parity predictor circuit.
References
- Prof. John Kimani “A Combinational Multiplier Using the Xilinx Spartan II FPGA”, Northeastern University, EECE 2160.
- Ms. R.S.Khond1, Prof.P.R.Indurkar2, Prof. P.R Lakhe3 “REVIEW ON DIFFERENT ERROR CORRECTION CODES”, 1Department of Electronics Engineering S.D. College Of Engg. 2Department of ENTC B.D. College Of Engg.,3 Department of Electronics Engineering S.D. College of Engineering Wardha, Maharashtra, India
- Siavash Bayat-Sarmadi, M. Anwar Hasan NOVEMBER 2009 “Concurrent Error Detection in Finite-Field Arithmetic Operations Using Pipelined and Systolic Architectures” Senior Member, IEEE, IEEE TRANSACTIONS ON COMPUTERS, VOL. 58, NO. 11.
- Heumpil Cho, JUNE 2009 "Adder and Multiplier Design in Quantum-Dot Cellular Automata", Member, IEEE, and Earl E. Swartzlander, Jr., Fellow, IEEE, IEEE TRANSACTIONS ON COMPUTERS, VOL. 58, NO. 6.
- M Mustafa, M R Beigh January 2013 "Design & implementation of quantum cellular automata based novel parity generator and checker circuits with minimum complexity and cell count" Indian journal of Pure & Applied Physics Vol.51.
- Kabiraj Sethi, Rutuparna Panda 2012 "An Improved Squaring Circuit for Binary Numbers", International Journal of Advanced Computer Science and Applications, Vol. 3, No.2.
- Jyoti Gupta, Amit Grover "A Comparative Performance Analysis of Various CMOS Design Techniques for Multiplier Circuits", Assistant Professor, Shaheed Bhagat Singh International Journal of Advanced Research in Computer and Communication Engineering Vol. 3, Issue 5, May 2014
- Dr. E. N. Ganesh 2010 "Implementation and simulation of arithmetic logic unit, shifter and Multiplier in Quantum Cellular automata technology.",(IJCSE) International Journal on Computer Science and Engineering Vol. 02, No. 05.
- Rahat Ullah, Jahangir Khan, Shahid Latif, Inayat Ullah September 2011 "Indication of Efficient Technique for Detection of Check Bits in Hamming Code", IJCSI International Journal of Computer Science Issues, Vol. 8, Issue 5, No 1.
- Ismo H¨anninen and Jarmo Takala, December 2007 "Binary Multipliers on Quantum-Dot Cellular Automata", FACTA UNIVERSITATIS (NIˇS)SER: ELEC. ENERG. vol. 20, no. 3.
- Subhasish Mitra and Edward J. McCluskey “WHICH CONCURRENT ERROR DETECTION SCHEME TO CHOOSE?”
- K.Walus, Wei Wang and Julliaen et al, 1999 “Quantum Cellular Automata adders” in Proc IEEE Nanotechnology conf, vol 3 page461- 463December 2004. I. Amlani. Digital logic gate using quantum-dot cellular automata. Science, 284:289.
- K. Walus 2002 “ATIPS laboratory QCA Designer homepage”, http://www.qcadesigner.ca, ATIPS Laboratory, University of Calgary, Canada.
Index Terms
Keywords