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Optimized High Performance 10T SRAM Cell Characterization

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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2016
Authors:
Arjun Singh Yadav, Sangeeta Nakhte
10.5120/ijca2016907964

Arjun Singh Yadav and Sangeeta Nakhte. Article: Optimized High Performance 10T SRAM Cell Characterization. International Journal of Computer Applications 134(5):29-33, January 2016. Published by Foundation of Computer Science (FCS), NY, USA. BibTeX

@article{key:article,
	author = {Arjun Singh Yadav and Sangeeta Nakhte},
	title = {Article: Optimized High Performance 10T SRAM Cell Characterization},
	journal = {International Journal of Computer Applications},
	year = {2016},
	volume = {134},
	number = {5},
	pages = {29-33},
	month = {January},
	note = {Published by Foundation of Computer Science (FCS), NY, USA}
}

Abstract

In this work, optimized Low power and high speed SRAM architecture based on ten transistor (10T) bit-cell is proposed. This cell obtains low static power and high speed read due to two independent read access mechanisms, which offers cascading of read driver. It also estimates read/write delay, read stability, write stability and compare the result with that of standard 6T, 9T and LP10T SRAM cell. The comparative study based on VDD and Temperature variation using simulation exhibits appreciable improvement in read delay and write SNM.

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Keywords

Standby Powers, Read Operation Delay, Write Operation Delay, Monte Carlo Simulation and Static Noise Margin.