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Reseach Article

Low Power and High Speed 13T SRAM Cell with Bit-Interleaving Capability

by Shivendra Kumar Sharma, Bhavana P. Shrivastava
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 141 - Number 11
Year of Publication: 2016
Authors: Shivendra Kumar Sharma, Bhavana P. Shrivastava
10.5120/ijca2016909859

Shivendra Kumar Sharma, Bhavana P. Shrivastava . Low Power and High Speed 13T SRAM Cell with Bit-Interleaving Capability. International Journal of Computer Applications. 141, 11 ( May 2016), 21-24. DOI=10.5120/ijca2016909859

@article{ 10.5120/ijca2016909859,
author = { Shivendra Kumar Sharma, Bhavana P. Shrivastava },
title = { Low Power and High Speed 13T SRAM Cell with Bit-Interleaving Capability },
journal = { International Journal of Computer Applications },
issue_date = { May 2016 },
volume = { 141 },
number = { 11 },
month = { May },
year = { 2016 },
issn = { 0975-8887 },
pages = { 21-24 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume141/number11/24829-2016909859/ },
doi = { 10.5120/ijca2016909859 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:43:16.029304+05:30
%A Shivendra Kumar Sharma
%A Bhavana P. Shrivastava
%T Low Power and High Speed 13T SRAM Cell with Bit-Interleaving Capability
%J International Journal of Computer Applications
%@ 0975-8887
%V 141
%N 11
%P 21-24
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper a low power single ended 13T SRAM cell has been proposed for bit inter-leaving application. A column aware scheme is used in the cell to achieve stable SRAM cell with better performance than the existing designs. The proposed SRAM cell exhibit robust read operation and better read performance with lower power consumption. This proposed 13T SRAM has been compared with standard 6T SRAM and existing 9T SRAM (with bit-interleaving capability) in term of Power consumption, Delay and Power Delay Product (PDP) at various supply voltages as 1.8V, 1.6V and 1.4V. The simulations are carried out on Cadence Virtuoso at 180nm CMOS technology and the simulation results are analyzed to verify the superiority of the proposed design over the existing designs. The proposed 13T SRAM proves to be better in terms of power and PDP at all the supply voltages. At 1.8V power saving by the proposed circuit is 72.46% compared to standard 6T SRAM cell and significant improvement is observed at other supply voltages also.

References
  1. W. R. E. Aly and M. A. Bayoumi, "Low-power cache design using 7T SRAM cell ", IEEE Trans. Circ. Sys. , vol. 54, no. 4,pp. 318-322, April 2007.
  2. S. A. Tawfik and V. Kursun, "Low power and roubst 7T dual-Vt SRAM circuit", in Proc. IEEE Int. Symp. Circ. Sys. , ISCAS 2008, Seatle, W A, USA, 2008, pp. 1452-1455.
  3. B.H. Calhoun, J.F. Ryan, S. Khanna, et al., “Flexible circuits and architectures for ultralow power”, Proc. IEEE , 2010 , vol. 98 , pp. 267–282.
  4. S. Hanson, B. Zhai, K. Bernstein, et al., “Ultralow-voltage, minimum-energy CMOS”, IBM J. Res. Develop ,vol.50 , pp. 469–490 , 2006.
  5. E. Seevinck et al., “Static-noise margin analysis of MOS SRAM cells,” IEEE J. Solid-State Circuits, vol. SC-22, no. 2, pp. 748–754, May 1987.
  6. Ik Joon Chang, Jae-Joon Kim, et al., “A 32 kb 10T sub-threshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS”, IEEE J. Solid-State Circuits vol. 44 , no. 2 , pp. 650–658 , Feb. 2009.
  7. Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsan, et al., “A single-ended disturbfree 9T subthreshold SRAM with cross-point data-aware write word-line structure, negative bit-line, and adaptive read operation timing tracing”, IEEE J. Solid-State Circuits vol. 47, no. 6 , pp. 1–14, June 2012 .
  8. Meng-Fan Chang, Shi-Wei Chang, Po-Wei Chou, et al., “A 130 mV SRAM with expanded write and read margins for subthreshold applications”, IEEE J. Solid-State Circuits vol. 46 , no.2, pp. 520–529 , Feb. 2011 .
  9. Ming-Hung Chang, Yi-Te Chiu, Wei Hwang, et al., “Design and Iso-area vmin analysis of 9T subthreshold SRAM with bit-interleaving scheme in 65-nm CMOS”, IEEE Trans. Circuits Syst.—II: vol. 59 , no.7 , pp. 429–433 , July 2012.
  10. Anh-Tuan Do, Jeremy Yung Shern Low, Joshua Yung Lih Low, et al., “An 8T differential SRAM with improved noise margin for bit-interleaving in 65 nm CMOS,” IEEE Trans. Circuits Syst.—I Regul.vol. 58, no. 6, pp. 1252–1263, June 2011.
  11. Koichi Takeda, Yasuhiko Hagihara, Yoshiharu Aimoto, et al., “A read-static noise-margin-free SRAM cell for low-VDD and high-speed applications”, IEEE J.Solid-State Circuits, vol. 41, no.1, pp. 113-121, Jan. 2006.
  12. Liang Wen , Zhikui Duan , Yi Li , Xiaoyang Zeng , “Analysis of a read disturb-free 9T SRAM cell with bit-interleaving capability” , Microelectronics Journal , vol. 45, pp. 815–824, mar. 2014.
  13. K. khare, R. Kar, D. Mandal, S.P. Ghosal, “Analysis of leakage current and leakage power reduction during write operation in CMOS SRAM cell” IEEE international conference on communication and signal processing, April 2014, pp. 523-527.
  14. J. Singh, 1. Mathew, and K. D. Pradhan, "A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies", in Proc. IEEE Int. SOC Conf. SOCC, 2008 , pp. 243-246.
  15. P. Hazucha, T. Karnik, and J. Maiz, et al., “Neutron soft error rate measurement in 90-nm CMOS process and scaling trends in SRAM from 0.25-um to 90-nm generation”, in: Proc. 2003 IEDM Technical Digest, 2003, pp. 21.5.1– 21.5.4.
Index Terms

Computer Science
Information Sciences

Keywords

SRAM cell Leakage Power Low Power Stability Bit-interleaving PDP.