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Performance Study of Energy Recovery Logic and Conventional CMOS Full Adder

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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2016
Authors:
Baljinder Kaur, Narinder Sharma
10.5120/ijca2016909887

Baljinder Kaur and Narinder Sharma. Performance Study of Energy Recovery Logic and Conventional CMOS Full Adder. International Journal of Computer Applications 142(8):31-35, May 2016. BibTeX

@article{10.5120/ijca2016909887,
	author = {Baljinder Kaur and Narinder Sharma},
	title = {Performance Study of Energy Recovery Logic and Conventional CMOS Full Adder},
	journal = {International Journal of Computer Applications},
	issue_date = {May 2016},
	volume = {142},
	number = {8},
	month = {May},
	year = {2016},
	issn = {0975-8887},
	pages = {31-35},
	numpages = {5},
	url = {http://www.ijcaonline.org/archives/volume142/number8/24918-2016909887},
	doi = {10.5120/ijca2016909887},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

In recent times, there is huge demand of low energy and low voltage in electronics industry. This low power dissipation is very useful in wireless operated devices and in consumer electronics market or battery operated devices. These low power circuits have ability to reduce the battery cells and reduction in these cells can enhance the uses of low weight and tiny size systems. Authors have designed the combinational circuit full adder using adiabatic method ECRL and also done comparison with traditional CMOS in this paper. The energy recovery logic ECRL is reversible logic and it can minimize the power up to 70-75.Authors have also done number of analysis on adiabatic methodology like altering the frequency and rise time and fall time of the circuit. All the results and calculations are simulated on s-edit using TANNER v.7 technology.

References

  1. Richa Singh,Anjali Sharma, “Power Efficient Design Of Multiplexer Based Compressor Using Adiabatic Logic”International Journal Of Computer Applications, pp:45-50, November 2013.
  2. Samik Samantha, “Study and Analysis Of Two Partially Adiabatic Inverters” International Conference On Communication, Circuits and Systems iC3S-2012, pp:17-19,2012.
  3. A.G Dickinson and J.S.denker ,"Adiabatic Dynamic Logic," IEEE. Journal of Solid-static Circuits, pp 311-315,1995.
  4. Ashish Raghuwanshi,Prof. Preet Jain, “An Efficient Adiabatic CMOS Circuit Design Approach For Low Power Applications” International Journal Of Electronics Communication and Computer Engineering,pp:1400-1406,Volume 4, 2013.
  5. Nikunj R.Patel,Sarman K Hadia, “Adiabatic Logic For Low Power Application Using Design 180nm Technology”,International Journal of Computer Trends and Technology,pp:800-804,April-2013.
  6. Sanjay Kumar 2009. Design Of Low Power CMOS Cell Structures Based On Adiabatic Switching Principle.M.techThesis.RegistrationNo.650861001,Thapar University.
  7. Ila Gupta, Neha Arora and B P Singh, “An Efficient Design of 2:1 Multiplexer and Its Application in 1-Bit Full Adder Cell”, International Journal of Computer Application and Its Application in 1 Bit Full Adder, Vol. 40, February 2012.
  8. Y. Moon and D. K. Jeong, “An Efficient Charge RecoveryLogic Circuit,” IEEE JSSC ,Vol.31, No. 04, pp. 514-522,April 1996.
  9. B.Dilli Kumar,M.Barathi, “Design Of EnergyEfficient Arithmetic Circuits Using Charge RecoveryAdiabatic Logic”, International Journal Of EngineeringTrends and Technology,pp:32-40, Volume 4-2013.
  10. Arun Kumar, Manoj Sharma, “Design and Analysis ofMux using Adiabatic Techniques ECRL andPFAL,”International Conferences on Advances InComputing, Communication and Infomatics, pp: 1341-1345, 2013.

Keywords

ECRL, CMOS, Full Adder. Adiabatic Logic