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Performance Study of Energy Recovery Logic and Conventional CMOS Full Adder

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2016
Baljinder Kaur, Narinder Sharma

Baljinder Kaur and Narinder Sharma. Performance Study of Energy Recovery Logic and Conventional CMOS Full Adder. International Journal of Computer Applications 142(8):31-35, May 2016. BibTeX

	author = {Baljinder Kaur and Narinder Sharma},
	title = {Performance Study of Energy Recovery Logic and Conventional CMOS Full Adder},
	journal = {International Journal of Computer Applications},
	issue_date = {May 2016},
	volume = {142},
	number = {8},
	month = {May},
	year = {2016},
	issn = {0975-8887},
	pages = {31-35},
	numpages = {5},
	url = {},
	doi = {10.5120/ijca2016909887},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}


In recent times, there is huge demand of low energy and low voltage in electronics industry. This low power dissipation is very useful in wireless operated devices and in consumer electronics market or battery operated devices. These low power circuits have ability to reduce the battery cells and reduction in these cells can enhance the uses of low weight and tiny size systems. Authors have designed the combinational circuit full adder using adiabatic method ECRL and also done comparison with traditional CMOS in this paper. The energy recovery logic ECRL is reversible logic and it can minimize the power up to 70-75.Authors have also done number of analysis on adiabatic methodology like altering the frequency and rise time and fall time of the circuit. All the results and calculations are simulated on s-edit using TANNER v.7 technology.


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ECRL, CMOS, Full Adder. Adiabatic Logic