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Design of Low Power Sense Amplifier based NAND Latch under 30nm Technology

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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2016
Authors:
K. Gavaskar, P. Kaviya Priya, M. Sukhanya
10.5120/ijca2016910106

K Gavaskar, Kaviya P Priya and M Sukhanya. Design of Low Power Sense Amplifier based NAND Latch under 30nm Technology. International Journal of Computer Applications 144(2):1-4, June 2016. BibTeX

@article{10.5120/ijca2016910106,
	author = {K. Gavaskar and P. Kaviya Priya and M. Sukhanya},
	title = {Design of Low Power Sense Amplifier based NAND Latch under 30nm Technology},
	journal = {International Journal of Computer Applications},
	issue_date = {June 2016},
	volume = {144},
	number = {2},
	month = {Jun},
	year = {2016},
	issn = {0975-8887},
	pages = {1-4},
	numpages = {4},
	url = {http://www.ijcaonline.org/archives/volume144/number2/25148-2016910106},
	doi = {10.5120/ijca2016910106},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

In electronics, a latch is a circuit that has two stable states and can be used to store information. Therefore latches can be memory devices and can store one bit of data as long as the device is powered. This paper mainly concentrated on the design of low power sense amplifier based NAND latch where sense amplifier is part of the read circuit that is used when data is read from the memory and amplify the voltage swing. An analytical model of different sense amplifier based NAND latch was designed and simulated using 30nm CMOS technology with various supply voltage. The NAND latch designed using low power Conventional Voltage Sense Amplifier is proposed in this paper. The simulation is carried out in SYNOPSYS EDA software under 30nm technology with different supply voltages.

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Keywords

Memory, Sense Amplifier, NAND latch, Low Power.