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Techniques for the Design of High Speed and Low Power MAC Unit: A Sate-of-the-art Review
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 148 - Number 13 |
| Year of Publication: 2016 |
| Authors: Anu, Prachi Chaudhary, Pawan Kumar Dahiya |
10.5120/ijca2016911245
|
Anu, Prachi Chaudhary, Pawan Kumar Dahiya . Techniques for the Design of High Speed and Low Power MAC Unit: A Sate-of-the-art Review. International Journal of Computer Applications. 148, 13 ( Aug 2016), 22-25. DOI=10.5120/ijca2016911245
Abstract
The multiplication operation is used in many parts of a digital system or digital computer, usually in signal processing, video/graphics and scientific computation. With advances in technology, various techniques have been developed to design multipliers, which offer high speed, low power consumption and lesser area. Thus making them suitable for various high speeds, low power compact VLSI implementations. These three parameters i.e. power, area and speed are always traded off. In this paper, different techniques used for efficient operations resulting in high speed and low power consumption are discussed. Such as parallelism, pipelining, modified booth algorithm (MBA), spurious power suppression technique (SPST), block enabling technique.
References
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