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A Result Analysis of ASIC Design of Reversible Multiplier Circuit

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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2017
Authors:
Anand Dayal, Himanshu Shekhar
10.5120/ijca2017913071

Anand Dayal and Himanshu Shekhar. A Result Analysis of ASIC Design of Reversible Multiplier Circuit. International Journal of Computer Applications 160(8):40-43, February 2017. BibTeX

@article{10.5120/ijca2017913071,
	author = {Anand Dayal and Himanshu Shekhar},
	title = {A Result Analysis of ASIC Design of Reversible Multiplier Circuit},
	journal = {International Journal of Computer Applications},
	issue_date = {February 2017},
	volume = {160},
	number = {8},
	month = {Feb},
	year = {2017},
	issn = {0975-8887},
	pages = {40-43},
	numpages = {4},
	url = {http://www.ijcaonline.org/archives/volume160/number8/27107-2017913071},
	doi = {10.5120/ijca2017913071},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

Reversible logic is very lots of in demand for the long term computing technologies as they are known to supply low power dissipation having its applications in Low Power, Quantum Computing, nanotechnology, and Optical Computing. during this paper, we have got given and implemented reversible Wallace signed multiplier circuit in ASIC through changed Baugh-Wooley approach using normal reversible logic gates/cells, based on complementary pass transistor logic and are valid with simulations, a layout vs. schematic check, and a design rule check.

References

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Keywords

Reversible logic gates, Reversible logic circuits, Quantum Computing Systems, Wallace Signed multiplier, Baugh-Wooley approach.