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Designing of Multiplier with Improved AHL

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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2017
Authors:
Ankita Gupta, Braj Bihari Soni, Puran Gaur
10.5120/ijca2017914233

Ankita Gupta, Braj Bihari Soni and Puran Gaur. Designing of Multiplier with Improved AHL. International Journal of Computer Applications 168(13):25-29, June 2017. BibTeX

@article{10.5120/ijca2017914233,
	author = {Ankita Gupta and Braj Bihari Soni and Puran Gaur},
	title = {Designing of Multiplier with Improved AHL},
	journal = {International Journal of Computer Applications},
	issue_date = {June 2017},
	volume = {168},
	number = {13},
	month = {Jun},
	year = {2017},
	issn = {0975-8887},
	pages = {25-29},
	numpages = {5},
	url = {http://www.ijcaonline.org/archives/volume168/number13/27945-2017914233},
	doi = {10.5120/ijca2017914233},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

The effects aging of digital circuits are came into the focused due to observations made with several experiments and researchers has start working towards making changes for the improvements in base paper architecture. The integrated device suffers with NBTI and PBTI due to CMOS semiconductor properties and it affects the working of different logic operations and in the same context here we have taken multiplier for consideration and working to develop delay efficient multiplier with aging aware design using adaptive hold logic which is modified in this work to reduce effective delay to speedup circuit logic. The simulation of experiments are conducted in Xilinx IDE 13.1.

References

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Keywords

Adaptive hold logic, row bypassing, column bypassing, Multiplier, Aging Effect, NBTI, PBTI, Delay Efficient