The week's pick
Random Articles
Reseach Article
Design and Implementation of Power and Area Efficient 3-Bit Flash ADC using GDI Technique
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 182 - Number 2 |
| Year of Publication: 2018 |
| Authors: Neetika Yadav, Preeti Kumari |
10.5120/ijca2018917452
|
Neetika Yadav, Preeti Kumari . Design and Implementation of Power and Area Efficient 3-Bit Flash ADC using GDI Technique. International Journal of Computer Applications. 182, 2 ( Jul 2018), 13-16. DOI=10.5120/ijca2018917452
Abstract
ADC (Analog to Digital Converter) is a device which converts analog values into digital numbers; analog values usually are in the form of voltages. Flash ADC, also called parallel ADC, is used where maximum sampling rate is required. Although this is the fastest ADC but its main disadvantage is that it consumes a lot of area and also dissipates a large amount of power because it is formed of a series of comparators which are connected with priority encoder. In this paper to overcome these disadvantages, the number of comparators are reduced by using multiplexers to generate the reference voltage which are designed with a new technique called GDI and by using this,a 3 bit flash ADC is designed by completely modifying the analog and digital parts. This architecture is then compared with the CMOS based ADC and TG based ADC. This architecture uses only 3 comparators for a 3 bit ADC. This 3-bit ADC is designed and simulated in Mentor Graphics Pyxis schematic tool with 1.8 V supply voltage and 180 nanometer technology.
References
- Sujatha Hiremath,Akshata Mathad, Amruta Hosur, Dr. Deepali Koppad, “Design of low power standard cells using full swing gate diffusion input” ,International Conference on Communication and Signal Processing (ICCSP), 2016.
- Rishab Goyal ,Sanjeev Sharma, “Design and Analysis Four Bit Hybrid Full Adder Cell using Gate Diffusion Input Technique and Domino Logic “, 4th IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics (UPCON), IEEE, Oct 26-28, 2017
- Gugulothu Saida, Shweta Meena , “Implementation of Low Power BCD Adder using Gate Diffusion Input Cell” ,International Conference on Communication and Signal Processing, IEEE, April 6-8, 2016
- Megha R, Pradeepkumar K A, “Implementation of Low Power Flash ADC by Reducing Comparators” International Conference on Communication and Signal Processing, IEEE April 2014.
- Chia-Nan Yeh and Yen-Tai Lai, “A Novel Flash Analog- to-Digital Converter” IEEE Journal 2008.
- Padmanabhan Balasubramanian, Johince John, “Low Power Digital design using modified GDI method” IEEE Journal 2006.
- Bui Van Hieu, Seunghyun Beak, Seunghwan Choi, Jongkook Seon, Taikyeong Ted. Jeong, “Thermometer-to-binary Encoder Circuit for Flash Analog-to-Digital Converter” International Conference on signal processing, IEEE 2010.
- Morgenshtein Fish, A.Wagner, “Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits” Very Large Scale Integration (VLSI) Systems, IEEE Journals 2002.
- Morgenshtein, Moreinis, Ginosar, “Asynchronous gate-diffusion-input (GDI) circuits” Very Large Scale Integration (VLSI) Systems, IEEE Journals 2004.
- G. Prajpat, A.Joshi, A.Jain,K.Verma, “Design of Low Power and High Speed 4-Bit Comparator Using Transmission Gate” International Conference on Machine Intelligence and Research Advancement, IEEE 2010
Index Terms
Keywords