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Reseach Article

Design and Implementation of Power and Area Efficient 3-Bit Flash ADC using GDI Technique

by Neetika Yadav, Preeti Kumari
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 182 - Number 2
Year of Publication: 2018
Authors: Neetika Yadav, Preeti Kumari
10.5120/ijca2018917452

Neetika Yadav, Preeti Kumari . Design and Implementation of Power and Area Efficient 3-Bit Flash ADC using GDI Technique. International Journal of Computer Applications. 182, 2 ( Jul 2018), 13-16. DOI=10.5120/ijca2018917452

@article{ 10.5120/ijca2018917452,
author = { Neetika Yadav, Preeti Kumari },
title = { Design and Implementation of Power and Area Efficient 3-Bit Flash ADC using GDI Technique },
journal = { International Journal of Computer Applications },
issue_date = { Jul 2018 },
volume = { 182 },
number = { 2 },
month = { Jul },
year = { 2018 },
issn = { 0975-8887 },
pages = { 13-16 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume182/number2/29733-2018917452/ },
doi = { 10.5120/ijca2018917452 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-07T01:10:10.852047+05:30
%A Neetika Yadav
%A Preeti Kumari
%T Design and Implementation of Power and Area Efficient 3-Bit Flash ADC using GDI Technique
%J International Journal of Computer Applications
%@ 0975-8887
%V 182
%N 2
%P 13-16
%D 2018
%I Foundation of Computer Science (FCS), NY, USA
Abstract

ADC (Analog to Digital Converter) is a device which converts analog values into digital numbers; analog values usually are in the form of voltages. Flash ADC, also called parallel ADC, is used where maximum sampling rate is required. Although this is the fastest ADC but its main disadvantage is that it consumes a lot of area and also dissipates a large amount of power because it is formed of a series of comparators which are connected with priority encoder. In this paper to overcome these disadvantages, the number of comparators are reduced by using multiplexers to generate the reference voltage which are designed with a new technique called GDI and by using this,a 3 bit flash ADC is designed by completely modifying the analog and digital parts. This architecture is then compared with the CMOS based ADC and TG based ADC. This architecture uses only 3 comparators for a 3 bit ADC. This 3-bit ADC is designed and simulated in Mentor Graphics Pyxis schematic tool with 1.8 V supply voltage and 180 nanometer technology.

References
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Index Terms

Computer Science
Information Sciences

Keywords

MUX TG GDI ADC DAC