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Reseach Article

Capability Aware Dynamic Load Balancer for Asymmetric NUMA Multicore Processors

by D.A. Mehta, Priyesh Kanungo
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 183 - Number 13
Year of Publication: 2021
Authors: D.A. Mehta, Priyesh Kanungo

D.A. Mehta, Priyesh Kanungo . Capability Aware Dynamic Load Balancer for Asymmetric NUMA Multicore Processors. International Journal of Computer Applications. 183, 13 ( Jul 2021), 20-28. DOI=10.5120/ijca2021921433

@article{ 10.5120/ijca2021921433,
author = { D.A. Mehta, Priyesh Kanungo },
title = { Capability Aware Dynamic Load Balancer for Asymmetric NUMA Multicore Processors },
journal = { International Journal of Computer Applications },
issue_date = { Jul 2021 },
volume = { 183 },
number = { 13 },
month = { Jul },
year = { 2021 },
issn = { 0975-8887 },
pages = { 20-28 },
numpages = {9},
url = { },
doi = { 10.5120/ijca2021921433 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
%0 Journal Article
%1 2024-02-07T01:16:42.099397+05:30
%A D.A. Mehta
%A Priyesh Kanungo
%T Capability Aware Dynamic Load Balancer for Asymmetric NUMA Multicore Processors
%J International Journal of Computer Applications
%@ 0975-8887
%V 183
%N 13
%P 20-28
%D 2021
%I Foundation of Computer Science (FCS), NY, USA

The different cores of state-of-the artmulticore processors are performance asymmetric: they are different in terms of their clock speeds and other capabilities. Such heterogeneous multicore processors pose challenges to existing Dynamic Load Balancers in achievingoptimum performance.A load balancer taking the load balancing related decisions assuming all cores to be homogeneous, introduces unnecessary overheads of time, does not exploit the capabilities of higher performance cores, and consequently fails to achieve the possible performance improvement.We, therefore, propose a Capability Aware Dynamic Load Balancer which performs efficient load balancing for asymmetric multicore processors by addressing the aforesaid issues. Considering the difference in clock speeds as the heterogeneity among different cores, the proposed load balancer improves the Turn Around Time of processes significantly as compared to Asymmetry unaware linux load balancer. The results of experimentation exhibit the performance gain in the range of 4-9%, for three different multicore systems having 32, 64 and 128 cores respectively.

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Index Terms

Computer Science
Information Sciences


Dynamic Load Balancing DLB Load Balancer NUMA Speed Core