Call for Paper - January 2024 Edition
IJCA solicits original research papers for the January 2024 Edition. Last date of manuscript submission is December 20, 2023. Read More

Integration and Performance Investigation of Multilevel Inverter with Half Bridge and Developed H-bridge Configurations

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2021
Mahwish Memon, Mukhtiar Ahmed Mahar, Aneeqa Sattar

Mahwish Memon, Mukhtiar Ahmed Mahar and Aneeqa Sattar. Integration and Performance Investigation of Multilevel Inverter with Half Bridge and Developed H-bridge Configurations. International Journal of Computer Applications 183(41):51-54, December 2021. BibTeX

	author = {Mahwish Memon and Mukhtiar Ahmed Mahar and Aneeqa Sattar},
	title = {Integration and Performance Investigation of Multilevel Inverter with Half Bridge and Developed H-bridge Configurations},
	journal = {International Journal of Computer Applications},
	issue_date = {December 2021},
	volume = {183},
	number = {41},
	month = {Dec},
	year = {2021},
	issn = {0975-8887},
	pages = {51-54},
	numpages = {4},
	url = {},
	doi = {10.5120/ijca2021921812},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}


This document introduces a new structure of power switches for Developed H-bridge with half bridge connected in cascade to provide increased of a nine-stepped output voltage inverter. The proposed model requires lesser number of switches and dc power sources, which results in decreasing the complexity of total cost of inverter. The multi-carrier pulse width modulation (LS-PD-PWM) method is designed to reduce the percentage of (THD) Total harmonic distortion. The output voltage THD is calculated using FFT analysis tool and is found to be 13.97%. The results taken by simulation are validated using MATLAB/SIMULINK software.


  1. E. B. a. G. B. G. J. Ebrahimi, "A new topology of cascaded multilevel converters with reduced number of components for high-voltage applications," in IEEE Trans. Power Electron, november 2011.
  2. R. S. A. N. S. S. H. H. E. B. Jagabar Sathik Mohamed Ali, "A new generalized multilevel converter topology based on cascaded connection of basic units," IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 7, no. 4, pp. 2498-2512, 2019.
  3. E. B. a. S. H. Hosseini, "Charge balance control methods for asymmetrical cascade multilevel converters," in International Conference on Electrical Machines and Systems (ICEMS), 2007.
  4. H. D. S. G. S. S. H. a. R. H. Vemuganti, "A Survey on Reduced Switch Count Multilevel Inverters.," IEEE Open Journal of the Industrial Electronics Society, vol. 55, 2021.
  5. M. A. M. A. U. a. A. S. L. Mahar, "Harmonic analysis of ac-dc topologies and their impacts on power systems.," Mehran University Research Journal of Engineering & Technology, vol. 1, pp. 173-178, 2011.
  6. M. A. F. N. a. A. I. Ali Mostafaeipour, "Identifying challenges and barriers for development of solar energy by using fuzzy best-worst method: A case study," Energy, vol. 226, 2021.
  7. S. A. a. S. L. Ebrahim Babaei, "A New General Topology for Cascaded Multilevel Inverters With Reduced," IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS,, vol. 61, 2014.
  8. A. H. A. S. L. M. A. M. A. A. S. I. A. S. Soomro, "Simulation-based Analysis of a Dynamic Voltage Restorer under Different Voltage Sags with the Utilization of a PI Controller," Engineering, Technology & Applied Science , vol. 4, pp. 5889-5895, 2020.
  9. N. P. K. Prabaharan, "Comparative analysis of symmetric and asymmetric reduced switch MLI topologies using unipolar pulse width modulation strategies," IET Power Electron.,, vol. 15, pp. 2808-2823, 2016.
  10. M. R. M. A. M. a. A. S. L. Qureshi, "Harmonic Analysis and Design of LC Filter for a Seven-level Asymmetric Cascaded Half Bridge Multilevel Inverter.," International Journal of Electrical Engineering & Emerging Technology , vol. 2, no. 3, pp. 52-58, 2020.
  11. J. I. S. V. a. L. G. F. Leon, "Multilevel converters: Control and modulation techniques for their operation and industrial applications," Proceedings of the IEEE, , vol. 105, no. 11, pp. 2066-2081, 2017.
  12. M. B. E. Kangarlu, "‘A generalized cascaded multilevel inverter using series connection of sub-multilevel inverters," IEEE Trans. Power Electron, vol. 28, pp. 625-635, 2013.
  13. T. A. R. V. S. a. J. B. P. G. A. Ramesh Babu, "Novel cascaded H-bridge sub-multilevel inverter with reduced switches towards low total harmonic distortion for photovoltaic application," International Journal of Ambient Energy, vol. 39, no. 2, pp. 117-121, 2018.
  14. I. K. E. B. R. c- Colak, "Review of multilevel voltage source," Energy Convers. Manage, vol. 52, p. 1114–1128, 2011.


Multilevel Inverter, POD-PWM, Cascaded H-Bridge inverter, MATLAB/Simulink Model.