The binary adder is a primary computational block in many arithmetic processors and digital signal processing applications. Artificial Neural Network (ANN)s validate a group of neuron particles to configure a feed-forward neural network, a perceptron that executes functionally accomplished basic logic gate operations and provides a re-programmable, re-configurable, extensible computing system and FPGA board to form ANNs and make analytical findings. Different methodologies are analyzed, such as ANNs, which are one of the most encouraging subsequent innovative designs, and researchers are exploring and enhancing different tradeoff characteristics such as delay, dynamic power dissipation, and area. With the constraint of purposeful computational time, the use of the intended style of software implementation provides the advantages of easy programming and low cost. Hardware implementation can be used to control the limits of software perception in neural networks. The proposed neural network hybrid adder’s major goal is to design a low-energy-delay device with a small footprint. In this paper, first consider the design of basic logic gates using neural networks followed by 1-bit hybrid full adder circuits, which are the primary components in computing. The hybrid adder designs are simulated and synthesized using Xilinx Vivado for the XC7Z020clg400-1 configurable device and implemented on the FPGA ZYBOZ7 board. The implementation findings reveal that, in comparison to Proposed Full Adder and single layer perceptron hybrid adder, the proposed multi-layer perceptron hybrid adder design achieved substantial refinement, with reductions of (60%, 60%) and (30.8%, 28.2%) in dynamic power dissipation and EDP, respectively.

ANN hybrid adder ANNs Dynamic Power dissipation EDP Perceptron