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Reseach Article

Design and Performance Assessment of Asymmetric Structure of Developed H-bridge Multilevel Inverter Configurated with Double-Level Circuit

by Saiqa Channa, Mukhtiar Ahmed Mahar, Abdul Sattar Larik
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 186 - Number 6
Year of Publication: 2024
Authors: Saiqa Channa, Mukhtiar Ahmed Mahar, Abdul Sattar Larik
10.5120/ijca2024923398

Saiqa Channa, Mukhtiar Ahmed Mahar, Abdul Sattar Larik . Design and Performance Assessment of Asymmetric Structure of Developed H-bridge Multilevel Inverter Configurated with Double-Level Circuit. International Journal of Computer Applications. 186, 6 ( Jan 2024), 14-19. DOI=10.5120/ijca2024923398

@article{ 10.5120/ijca2024923398,
author = { Saiqa Channa, Mukhtiar Ahmed Mahar, Abdul Sattar Larik },
title = { Design and Performance Assessment of Asymmetric Structure of Developed H-bridge Multilevel Inverter Configurated with Double-Level Circuit },
journal = { International Journal of Computer Applications },
issue_date = { Jan 2024 },
volume = { 186 },
number = { 6 },
month = { Jan },
year = { 2024 },
issn = { 0975-8887 },
pages = { 14-19 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume186/number6/33074-2024923398/ },
doi = { 10.5120/ijca2024923398 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-07T01:29:53.347720+05:30
%A Saiqa Channa
%A Mukhtiar Ahmed Mahar
%A Abdul Sattar Larik
%T Design and Performance Assessment of Asymmetric Structure of Developed H-bridge Multilevel Inverter Configurated with Double-Level Circuit
%J International Journal of Computer Applications
%@ 0975-8887
%V 186
%N 6
%P 14-19
%D 2024
%I Foundation of Computer Science (FCS), NY, USA
Abstract

A single-stage thirteen-level MLI is suggested in this paper based on the developed Hybrid bridge MLI configured with the double-level circuit. Though the concept of a double-level circuit was already introduced it is still not utilized. This topology will not only lessen the number of devices but also increase the output of an inverter twice that of the conventional cascaded hybrid bridge multilevel inverter. The purpose of this network topology is to enhance the output of the Multilevel inverter reduce the component count of devices used and utilize the concept of double level circuit. A pulse width modulation with a Phase disposition technique is used with the asymmetric structure of three DC sources V1=12, V2=24, and V3=48 to obtain a greater number of levels. The design of this suggested topology is done by using MATLAB software. An analysis is also carried out using the FFT tool in MATLAB software.

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Index Terms

Computer Science
Information Sciences

Keywords

Developed H-bridge Asymmetric Double level circuit Reduced device count.