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Reseach Article

Design and Performance Assessment of Asymmetric Structure of Developed H-bridge Multilevel Inverter Configurated with Double-Level Circuit

by Saiqa Channa, Mukhtiar Ahmed Mahar, Abdul Sattar Larik
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 186 - Number 6
Year of Publication: 2024
Authors: Saiqa Channa, Mukhtiar Ahmed Mahar, Abdul Sattar Larik
10.5120/ijca2024923398

Saiqa Channa, Mukhtiar Ahmed Mahar, Abdul Sattar Larik . Design and Performance Assessment of Asymmetric Structure of Developed H-bridge Multilevel Inverter Configurated with Double-Level Circuit. International Journal of Computer Applications. 186, 6 ( Jan 2024), 14-19. DOI=10.5120/ijca2024923398

@article{ 10.5120/ijca2024923398,
author = { Saiqa Channa, Mukhtiar Ahmed Mahar, Abdul Sattar Larik },
title = { Design and Performance Assessment of Asymmetric Structure of Developed H-bridge Multilevel Inverter Configurated with Double-Level Circuit },
journal = { International Journal of Computer Applications },
issue_date = { Jan 2024 },
volume = { 186 },
number = { 6 },
month = { Jan },
year = { 2024 },
issn = { 0975-8887 },
pages = { 14-19 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume186/number6/33074-2024923398/ },
doi = { 10.5120/ijca2024923398 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-07T01:29:53.347720+05:30
%A Saiqa Channa
%A Mukhtiar Ahmed Mahar
%A Abdul Sattar Larik
%T Design and Performance Assessment of Asymmetric Structure of Developed H-bridge Multilevel Inverter Configurated with Double-Level Circuit
%J International Journal of Computer Applications
%@ 0975-8887
%V 186
%N 6
%P 14-19
%D 2024
%I Foundation of Computer Science (FCS), NY, USA
Abstract

A single-stage thirteen-level MLI is suggested in this paper based on the developed Hybrid bridge MLI configured with the double-level circuit. Though the concept of a double-level circuit was already introduced it is still not utilized. This topology will not only lessen the number of devices but also increase the output of an inverter twice that of the conventional cascaded hybrid bridge multilevel inverter. The purpose of this network topology is to enhance the output of the Multilevel inverter reduce the component count of devices used and utilize the concept of double level circuit. A pulse width modulation with a Phase disposition technique is used with the asymmetric structure of three DC sources V1=12, V2=24, and V3=48 to obtain a greater number of levels. The design of this suggested topology is done by using MATLAB software. An analysis is also carried out using the FFT tool in MATLAB software.

References
  1. Memon, A. J., Mahar, M. A., Larik, A. S., & Shaikh, M. M. (2023). A comprehensive review of reduced device Count multilevel inverters for PV systems. Energies, 16(15), 5638.
  2. Adly, A. R., Abdul-Hamid, H. Y., Elhussiny, A., Zaky, M. S., & El-Kholy, E. E. (2023, February). A Brief Review of the Conventional and Multilevel Inverters Topologies. In 2023 IEEE Conference on Power Electronics and Renewable Energy (CPERE) (pp. 1-8). IEEE.
  3. NV, V. K. (2023). A comprehensive survey on reduced switch count multilevel inverter topologies and modulation techniques. Journal of Electrical Systems and Information Technology, 10(1), 1-24.
  4. Memon, R., Mahar, M. A., Larik, A. S., & Shah, S. A. A. (2023). Design and Performance Analysis of New Multilevel Inverter for PV System. Sustainability, 15(13), 10629.
  5. Prabaharan, N., & Palanisamy, K. (2016). Analysis and integration of multilevel inverter configuration with boost converters in a photovoltaic system. Energy Conversion and Management, 128, 327-342.
  6. Memon, M., Mahar, M. A., & Sattar, A. Integration and Performance Investigation of Multilevel Inverter with Half Bridge and Developed H-bridge Configurations. International Journal of Computer Applications, 975, 8887.
  7. Mahar, M.A., Uqaili, M.A. and Larik, A.S., 2011. Harmonic analysis of ac-dc topologies and their impacts on power systems. Mehran University Research Journal of Engineering & Technology, 30(1), pp.173-178.
  8. Qureshi, M.R., Mahar, M.A. and Larik, A.S., 2020. Harmonic Analysis and Design of LC Filter for a Seven-level Asymmetric Cascaded Half Bridge Multilevel Inverter. International Journal of Electrical Engineering & Emerging Technology, 3(2), pp.52-58.
  9. Babaei, E., Alilu, S., & Laali, S. (2013). A new general topology for cascaded multilevel inverters with a reduced number of components based on developed H-bridge. IEEE Transactions on Industrial Electronics, 61(8), 3932-3939..
  10. Alishah, R. S., Hosseini, S. H., Babaei, E., & Sabahi, M. (2016). Optimal design of new cascaded switch-ladder multilevel inverter structure. IEEE Transactions on Industrial Electronics, 64(3), 2072-2080.
  11. Prabaharan, N., & Palanisamy, K. (2017). Analysis of cascaded H‐bridge multilevel inverter configuration with double-level circuit. IET Power Electronics, 10(9), 1023-1033.
  12. ]. Babaei, E., Laali, S., & Alilu, S. (2014). Cascaded multilevel inverter with series connection of novel H-bridge basic units. IEEE transactions on industrial electronics, 61(12), 6664-6671.
  13. Khasim, S. R., & Dhanamjayulu, C. (2022). Design and implementation of asymmetrical multilevel inverter with reduced components and low voltage stress. IEEE Access, 10, 3495-3511.
  14. Ponraj, R. P., Sigamani, T., & Subramanian, V. (2021). A developed H-bridge cascaded multilevel inverter with reduced switch count. Journal of Electrical Engineering & Technology, 16, 1445-1455.
  15. Memon, S. (2023). Performance Investigation of Stand-alone Photovoltaic System with Three Phase Developed H-Bridge Multilevel Inverter. International Journal of Electrical Engineering & Emerging Technology, 6(1), 24-30.
  16. Dhanamjayulu, C., & Girijaprasanna, T. (2023). Experimental Implementation of Cascaded H-Bridge Multilevel Inverter with an Improved Reliability for Solar PV Applications. International Transactions on Electrical Energy Systems, 2023.
  17. a reduced switch Count. In 2021 IEEE Industrial Electronics and Applications Conference (IEACon) (pp. 103-107). IEEE.
  18. Memon, R., Mahar, M. A., & Larik, A. S. (2023). An asymmetrical multilevel inverter with low voltage stress and fewer components for a photovoltaic system.
  19. Ali, J. S. M., Almakhles, D. J., Ibrahim, S. A., Alyami, S., Selvam, S., & Bhaskar, M. S. (2020). A generalized multilevel inverter topology with reduction of total standing voltage. IEEE Access, 8, 168941-168950.
  20. Arif, M. S. B., Sarwer, Z., Siddique, M. D., Md. Ayob, S., Iqbal, A., rfe IVKM& Mekhilef, S. (2021). Asymmetrical multilevel inverter topology low total standing voltage and reduced switches count. International Journal of Circuit Theory and Applications, 49(6), 1757
Index Terms

Computer Science
Information Sciences

Keywords

Developed H-bridge Asymmetric Double level circuit Reduced device count.