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Study of 32-bit RISC Processor Architecture and VHDL FPGA Implementation 32-bit Matrix Manipulation

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International Journal of Computer Applications
© 2011 by IJCA Journal
Number 1 - Article 1
Year of Publication: 2011
Authors:
Vandana S. Shah
Dr. R. V. Kshirsagar
10.5120/3953-5432

Vandana S Shah and Dr. R V Kshirsagar. Article: Study of 32-bit RISC Processor Architecture and VHDL FPGA Implementation 32-bitMatrix Manipulation. International Journal of Computer Applications 32(3):50-55, October 2011. Full text available. BibTeX

@article{key:article,
	author = {Vandana S. Shah and Dr. R. V. Kshirsagar},
	title = {Article: Study of 32-bit RISC Processor Architecture and VHDL FPGA Implementation 32-bitMatrix Manipulation},
	journal = {International Journal of Computer Applications},
	year = {2011},
	volume = {32},
	number = {3},
	pages = {50-55},
	month = {October},
	note = {Full text available}
}

Abstract

Present title discloses a distinctive method to cram the processor behavior while dealing with the multifaceted task of matrix manipulation. System facilitates this distinct feature by allowing user to input the data in suitable form and observe the output using suitable display devices. [5] System is build around high performance VLSI technology. Matrix manipulation is on the whole parallel architecture of logical expressions. VLSI when implemented using High Performance Gate Arrays becomes most suitable for implementing parallel architecture. [6]

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