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Article:Design of AHB protocol block for Advanced Microcontrollers

by Rishabh Singh Kurmi, Shruti Bhargava, Ajay Somkuwar
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 32 - Number 8
Year of Publication: 2011
Authors: Rishabh Singh Kurmi, Shruti Bhargava, Ajay Somkuwar
10.5120/3924-5543

Rishabh Singh Kurmi, Shruti Bhargava, Ajay Somkuwar . Article:Design of AHB protocol block for Advanced Microcontrollers. International Journal of Computer Applications. 32, 8 ( October 2011), 23-29. DOI=10.5120/3924-5543

@article{ 10.5120/3924-5543,
author = { Rishabh Singh Kurmi, Shruti Bhargava, Ajay Somkuwar },
title = { Article:Design of AHB protocol block for Advanced Microcontrollers },
journal = { International Journal of Computer Applications },
issue_date = { October 2011 },
volume = { 32 },
number = { 8 },
month = { October },
year = { 2011 },
issn = { 0975-8887 },
pages = { 23-29 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume32/number8/3924-5543/ },
doi = { 10.5120/3924-5543 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:18:39.222281+05:30
%A Rishabh Singh Kurmi
%A Shruti Bhargava
%A Ajay Somkuwar
%T Article:Design of AHB protocol block for Advanced Microcontrollers
%J International Journal of Computer Applications
%@ 0975-8887
%V 32
%N 8
%P 23-29
%D 2011
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The AMBA Advanced high performance bus (AHB) protocol design acts as an interface between two different IP cores. In this work initially the investigation on the AHB is carried out and the basic commands and its working are identified based on which the signal flow diagram and the specifications are developed for designing the AMBA-AHB using VHDL. In this paper we propose the design and implementation of a flexible arbiter scheme for the AHB busmatrix based on burst operation. Basically, AHB burst operation is that a sequence of operation happens with respect to the size given and it supports only three burst sizes. The size is acting as one of the input to the master during the burst operation and after each burst operation, the master or slave will go to the IDLE stage. The AHB design contains basic blocks such as master and slave and the working of these blocks based on arbitration scheme. According to arbitration scheme only one master can Access the bus at any one time. Multiplexer and Decoders are used to selects the appropriate signals between master and slaves that are involved in the transfer. This AMBA-AHB protocol can be adopted in all the applications provided the design should be an AHB compliant.

References
  1. Soo Yun Hwang, Dong Soo Kang, Hyeong Jun Park, and Kyoung Son Jhang, Member, IEEE “Implementation of a self motivated arbitration scheme for the multilayer AHB busmatrix “ VOL. 18, NO. 5, MAY 2010 IEEE .
  2. Rishabh Singh Kurmi, Shruti Bhargava “ Implementation of an AMBA Advanced High performance Bus Protocol IP Block” IJECCE , June 2011, Vol.1, Issue 1, no. 2.
  3. S. Y. Hwang, K. S. Jhang, H. J. Park, Y. H. Bae, and H. J. Cho, “An ameliorated design method of ML-AHB busmatrix,” ETRI J., vol. 28, no. 3, pp. 397–400, Jun. 2006.
  4. ARM, “AHB Example AMBA System,” 2001
  5. Online. Available: http:// www.arm.com/products/solutions
  6. IBM, New York, “32-bit Processor Local Bus Architecture Specification,” 2001
  7. N.-J. Kim and H.-J. Lee, “Design of AMBA wrappers for multipleclock operations,” in Proc. Int. Conf. ICCCAS, Jun. 2004, vol. 2, pp. 1438–1442.
  8. D. Flynn, “AMBA: Enabling reusable on-chip designs,” IEEE Micro, vol. 17, no. 4, pp. 20–27, Jul./Aug. 1997 1http://www.arm.com/products/solutions/axi_spec.html accessed Feb. 2008.
  9. S. Y. Hwang, H.-J. Park and K.-S. Jhang,“Performance analysis of slave-side arbitration schemes for the multi-layer AHB busmatrix,” J.KISS, Comput. Syst. Theory, vol. 34, no. 5, pp. 257–266, Jun. 2007.
  10. C. H. Pyoun, C. H. Lin, H. S. Kim, and J. W. Chong, “The efficient bus arbitration scheme in SoC environment,” in Proc. Int. Conf. SoC Real-Time Appl. Jul. 2003, pp. 311–315.
  11. K. Lahiri, A. Raghunathan, and G. Lakshminarayana, “The LOTTERYBUS on-chip communication architecture,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 6, pp. 596–608, Jun. 2006.
  12. S. Y. Hwang, H. J. Park, and K. S. Jhang, An Efficient Implementation Method of Arbiter for the ML-AHB Busmatrix. Berlin, Germany: Springer-Verlag, May 2007, vol. 4523, LNCS, pp. 229–240.
  13. Douglas l. perry, VHDL Programming.
  14. E Simon, An embedded design primer, pearson education.
  15. Rajkamal Microcontroller, ARM processor, pearson education. www.pearson.co.in.
Index Terms

Computer Science
Information Sciences

Keywords

AHB busmatrix Arbiter System on Chip FSM for master and slave Master and slave side arbitration IP VHDL