CFP last date
20 May 2024
Call for Paper
June Edition
IJCA solicits high quality original research papers for the upcoming June edition of the journal. The last date of research paper submission is 20 May 2024

Submit your paper
Know more
The week's pick
Responsive image
Enhancing Privacy Preservation: Multi-Attribute Protection with P-Sensitive K-Anonymity

Twinkle Patel Kiran Amin
Random Articles
Reseach Article

Analysis of Performance factors for PLL based Frequency Synthesizers for Wireless Applications and Impact on Overall Performance

by P. Venkateswararao, K. S. Ramesh
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 42 - Number 10
Year of Publication: 2012
Authors: P. Venkateswararao, K. S. Ramesh
10.5120/5729-7799

P. Venkateswararao, K. S. Ramesh . Analysis of Performance factors for PLL based Frequency Synthesizers for Wireless Applications and Impact on Overall Performance. International Journal of Computer Applications. 42, 10 ( March 2012), 20-23. DOI=10.5120/5729-7799

@article{ 10.5120/5729-7799,
author = { P. Venkateswararao, K. S. Ramesh },
title = { Analysis of Performance factors for PLL based Frequency Synthesizers for Wireless Applications and Impact on Overall Performance },
journal = { International Journal of Computer Applications },
issue_date = { March 2012 },
volume = { 42 },
number = { 10 },
month = { March },
year = { 2012 },
issn = { 0975-8887 },
pages = { 20-23 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume42/number10/5729-7799/ },
doi = { 10.5120/5729-7799 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:30:59.068642+05:30
%A P. Venkateswararao
%A K. S. Ramesh
%T Analysis of Performance factors for PLL based Frequency Synthesizers for Wireless Applications and Impact on Overall Performance
%J International Journal of Computer Applications
%@ 0975-8887
%V 42
%N 10
%P 20-23
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper presents the PLL based Frequency Synthesizers, which are used in modern devices for generating wide range of frequencies. The Performance depends on several factors such as phase noise, spurious outputs, loop bandwidth and lock time. The parameters loop bandwidth and lock time are inter-related which are inversely proportional to each other is simulated and the results are given. The Phase Noise for the VCO depends on the frequency range in which it is used and given by Lesson's equation. It varies linearly and L-Band and higher frequencies but varies at 6dB per octave at lower frequencies in hundreds of MHz or tenths of GHz. The results are simulated in MATLAB and presented in this paper.

References
  1. Shashikant shrimali,Direct Digital Frequency Synthesizer, thesis, Texas Tech University, May 2007
  2. V. Valenta, G. Baudoin, "Phase Noise Analysis of PLL Based Frequency Synthesizers for Multi-Radio Mobile Terminals", IEEE vol. 50, Issue 2, pp. 429-432, 2010
  3. Ken Holladay, "Design a PLL for a specific Loop Bandwidth," Fujitsu Microelectronics, Oct 2000
  4. Curtin,Mike and paul O'Brien,"Phase Locked Loops for high-frequency receivers and transmitters-part 3", Analog Dialogue,33-7,1999
  5. Banerjee,Dean"PLLPerformance,Simulation and Design" 4th edition Publishing, 2006 stand ISBN – 10: 1598581341.
  6. D. B. Leeson, "A Simplified model of feedback oscillator noise", IEEE Volume 42, pp. 329-33,Feb 1965
Index Terms

Computer Science
Information Sciences

Keywords

Frequency Synthesizers Phase Noise Lesson's Equation

Powered by PhDFocusTM