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Design of Low Power RISI Processor by Applying Clock Gating Technique
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 43 - Number 20 |
| Year of Publication: 2012 |
| Authors: J. Ravindra, T. Anuradha |
10.5120/6223-8819
|
J. Ravindra, T. Anuradha . Design of Low Power RISI Processor by Applying Clock Gating Technique. International Journal of Computer Applications. 43, 20 ( April 2012), 38-42. DOI=10.5120/6223-8819
Abstract
Power has become a primary consideration during hardware design. Dynamic power can contribute up to 50% of the total power dissipation. Clock-gating is the most common RTL optimization for reducing dynamic power. Effective clock-gating implementation requires skilful application and comprehensive verification. Clock-gating support adds additional logic to the existing synchronous circuit to prune the clock tree, thus disabling the portions of the circuitry that are not in use. Here in this project designed and developed efficient data path and control units of an 8-bit microprocessor and clock gating technique applied to designed units. RTL clock-gating algorithms can be grouped into three categories: system-level, sequential and combinational. System-level clock-gating stops the clock for an entire block, effectively disabling all functionality. On the contrary, combinational and sequential clock-gating selectively suspend clocking while the block continues to produce output. In typical designs, combinational clock-gating can reduce dynamic power by about 5-to-10%. On the other hand sequential clock-gating can save significant power, typically reducing switching activity by 15-to-25% on a given block. Thus, different RTL techniques are used to reduce the power dissipation of a processor. The whole paper captured in VHDL and implemented on targeted FPGA chip and observed the power using Xilinx Xpower tool
References
- A Clock Gating Circuit for Globally Asynchronous Locally Synchronous Systems, Jonas Carlsson, Kent Palmkvist, and Lars Wanhammar Department of Electrical Engineering, Linkopings universitet SE-58 1 83 Linkoping Sweden
- AnEnergyEfic'ientHalf-tat"ic Cock-Gating D-Type Flip-Flop, Wing-Shan Tam, Oi-Ying Wong, Ka-Yan Mok, Chi-Wah Kok, Hei Wong
- A Novel Clock Distribution and Dynamic De-skewing Methodology, Ajun Kapoor* Nikhil Jayakumar' Sunil P Khatri'. * Department of EE, Texas A&M University, College Station TX 77843. * Department of ECE, University of Colorado, Boulder, CO 80309.
- Adaptive Clock Gating Technique for Low Power IP Core in SoC Design a. Xiaotao Chang 1,2, Mingming Zhang1,2, Ge Zhang1, Zhimin Zhang 1, Jun Wang1,21(Institute of Computing Technology, Chinese Academy of Sciences, Beijing, 100080, CHINA) 2(Graduate School of Chinese Academy of Sciences, Beijing, 100039, CHINA)
- CLOCK GATING ARCHITECTURES FOR FPGA POWER REDUCTION, Safeen Huda, Muntasir Mallick, Jason H. Anderson, Dept. of ECE, Univ. of Toronto, Toronto, ON Canada, e-mail: {safeen. huda, muntasir. mallick, jason. anderson}@utoronto. ca
- Gated Clock Routing for Low-Power Microprocessor Design, Jaewon Oh and Massoud Pedram, Senior Member, IEEE. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 6, JUNE 2001
- LANG, T. , MUSOLL, F , and CORTADELLA, J. : 'Individual flip-flops with gated clocks for low power datapaths', IEEE Trans. Circuits S y ~ tI. I , 1997, 44,( 6), pp. 507 516
- Low Power VLSI Design and Technology edited by G K Yeap (Motorola) & F N Najm (Univ. Illinois, Urban–Champaign)
- Logic Synthesis for Low Power VLSI Designs by Iman, Sasan, Pedram, Massoud
- Low-power digital VLSI design: circuits and systems by Abdellatif Bellaouar, Mohamed I. Elmasry
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