The week's pick
Random Articles
Reseach Article
Optimization of Chip Interconnect Area by using Interconnect Length and Width
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 5 - Number 3 |
| Year of Publication: 2010 |
| Authors: Dr.Y.Venkatarami Reddy, D.Venkata Vara Prasad |
10.5120/897-1271
|
Dr.Y.Venkatarami Reddy, D.Venkata Vara Prasad . Optimization of Chip Interconnect Area by using Interconnect Length and Width. International Journal of Computer Applications. 5, 3 ( August 2010), 21-26. DOI=10.5120/897-1271
Abstract
This paper presents methodologies that provide better correlation between the apriori and posteriori estimation of interconnect length, width, area and power. A method to generate random realistic benchmark circuits for analysis is implemented. A prediction model that predicts the length, width, area and power of the benchmark circuit is developed. The net list is passed through the placement and routing phases to obtain the actual length. From the estimated length, the width, area and power are estimated. The effectiveness of the prediction technique used is validated from the results obtained. We postulate that the predicted area which comes out with a smaller error percentage than predicted length can be used as a termination condition in Simulated Annealing for placement. Results are compared for proving optimization with Lagrange’s Method.
References
- “Circuit level netlist generation”, US Patent 5384710 -January, 1995.
- J. Darnauer and W. W. Dai, “A Method for Generating Random Circuitsand its Application to Routability Measurement”, In Proc. of Intl. Symp.on FPGAs, pp. 66-72, Feb 1996.
- M. D. Hutton, J. P. Grossman, J. S. Rose and D. Corneil, “Characterization and Parameterized Random Generation of Digital Circuits”, IEEE Trans. CAD, Vol. 17, No. 10, pp.955-966, Oct 1998.
- M. D. Hutton, J. S. Rose and D. Corneil, “Automatic Generation of Synthetic Sequential Benchmark Circuits,” IEEE Trans. CAD, Vol. 21, No. 8, pp. 928-940, Aug 2002.
- J. Pistorius, E. Legai and M. Minoux, “PartGen: A Generator of Very Large Circuits to Benchmark the Partitioning of FPGAs”, IEEE Trans. CAD, Vol. 19, No. 11, Nov 2000.
- D. Stroobandt, P. Verplaetse and J. V. Campenhout, “Generating Synthetic Benchmark Circuits for Evaluating CAD Tools”, IEEE Trans.CAD, Vol. 19, No. 9, pp. 1011-1022, Sep 2000.
- P. Verplaetse, J. V. Campenhout and D. Stroobandt, “On Synthetic Benchmark Generation Methods”, In Proc. Of ISCAS, Vol. IV, pp. 213-216, May 2000.
- B. S. Landman and R. L. Russo, “On a Pin versus Block Relationship for Partitions of Logic Graphs”, IEEE Trans. on Compute., pp. 1469-1479, 1971.
- Tao Wan and Malgorzata Chrzanowska-Jeske, “Generating Random Benchmark Circuits for Floorplanning”, ISCAS, IEEE 2004.
- Donath, W., “Placement and average interconnection lengths of computer logic”, Circuits and Systems, IEEE Transactions on Volume 26, Issue 4, Apr 1979.
- “Toward the accurate prediction of placement wire length distributions in VLSI circuits”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems,Volume 12 , Issue 4 (April 2004).
- “Individual wire-length prediction with application to timing-driven placement”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 12 , Issue 10 (October 2004).
- “Getting more out of Donath's hierarchical model for interconnect prediction”, International Workshop on System-Level Interconnect Prediction, Proceedings of the 2002.
- Qinghua Liu, Marek-Sadowska. M., “Semi-individual wire-length prediction with application to logic synthesis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions, April 2006.
- D.V.V. Prasad, Y.V. Rddy and V.K. Pandey,“A Unique Prediction Model of the Interconnect Geometry for a Full-Custom Design Style”, Journal of Applied Sciences, 2008.
- Xiao-Chun Li, Jun-Fa Mao, Hui-Fen Huang, and Ye Liu, “Global Interconnect Width and Spacing Optimization for Latency, Bandwidth and Power Dissipation”, IEEE Transactions on Electron Devices, Vol. 52, No. 10, Oct 2005.
- K.Banerjee and A.Mehrotra,”Analysis of on-chip Inductance Effects for Distributed RLC Interconnects”,IEEE Trans.Computer-aided Design Integer circuits Syst., Vol21,no.8,pp.904-915, Aug 2002.
- Mandeep Bamal,Evelyn Grossar and Karen Maex “Interconnect WidthSelection for Deep Submicron Designs Using the Table Lookup Method”, ACM, 2004.
- Naveed Sherwani , “Algorithms For VLSI Physical Design Automation”, 1999.
- D. Pamunuwa, L.R. Zheng, and H. Tenhunen, “Optimising bandwidth over deep sub-micron interconnect,” in Proc. IEEE Int. Symp. Circuits Syst., 2002, pp. IV/193–IV/196.
- A. Naeemi, R. Venkatesan, and J. D. Meindl, “Optimal global interconnects for GSI,” IEEE Trans. Electron Devices, vol. 50, no. 4,pp.980–987, Apr. 2003.
- K. Shahookar and P. Mazumder, “VLSI Cell Placement Techniques”, ACM Computing Surveys, Vol. 23, No. 2, June 1991.
- Iris Hui-Ru Jiang, Yao-Wen Chang, Member, IEEE, and Jing-Yang Jou, Member, IEEE “Crosstalk-Driven Interconnect Optimization by Simultaneous Gate and Wire Sizing” ieee transactions on computer-aided design of integrated circuits and systems, vol. 19, no. 9, september 2000
Index Terms
Keywords