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Reseach Article

Power Efficient Design of Polar Code

by Sapna R. Makvana, Brijesh Vala
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 87 - Number 7
Year of Publication: 2014
Authors: Sapna R. Makvana, Brijesh Vala

Sapna R. Makvana, Brijesh Vala . Power Efficient Design of Polar Code. International Journal of Computer Applications. 87, 7 ( February 2014), 35-39. DOI=10.5120/15223-3735

@article{ 10.5120/15223-3735,
author = { Sapna R. Makvana, Brijesh Vala },
title = { Power Efficient Design of Polar Code },
journal = { International Journal of Computer Applications },
issue_date = { February 2014 },
volume = { 87 },
number = { 7 },
month = { February },
year = { 2014 },
issn = { 0975-8887 },
pages = { 35-39 },
numpages = {9},
url = { },
doi = { 10.5120/15223-3735 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
%0 Journal Article
%1 2024-02-06T22:05:20.427582+05:30
%A Sapna R. Makvana
%A Brijesh Vala
%T Power Efficient Design of Polar Code
%J International Journal of Computer Applications
%@ 0975-8887
%V 87
%N 7
%P 35-39
%D 2014
%I Foundation of Computer Science (FCS), NY, USA

Polar codes are the family of the codes which are first ones to achieve channel capacity of any binary discrete memory less channel (B-DMC) with an explicit construction. The method relates with polar codes, channel polarization and encoding & decoding of polar code is considered that in the live structure of polar code when BER gets increase, channel capacity is satisfied but overall power of data transmition in channel gets increase. So here in this analysis the main issue is related with the power consumption. Encoding & decoding construction of polar codes is based on XOR-XNOR gates. The XOR-XNOR circuits' design which uses 6 transistors instead of conventional structure is designed and it is suitable for low-voltage and low-power application by achieving lower delay, power consumption and power-delay product (PDP). So by using this design phenomenon of XOR-XNOR gate it is possible to construct power efficient encoding and decoding of polar codes.

  1. Ahmed Elshahawy, Bahram Honary "An overview on Channel Polarization and Polar Codes" ISBN: 978-1-902560-26-7 © 2012 PGNet
  2. Peter Trifonov "Efficient Design and Decoding Of Polar Codes", Member, IEEE IEEE Transactions On Communications, Vol. 60, No. 11, November 2012
  3. Nabihah Ahmad Rezaul Hasan "A New Design of XOR-XNOR gates for low power Application" International Conference on Electronic Devices, Systems & Applications (ICEDSA), 2011
  4. Leroux, C "Hardware architectures for successive cancellation decoding for polar code" by. McGill Univ. , Montreal, QC, Canada, 978-1-4577-0539-©2012 IEEE
  5. ] Satish Babu Korada, Member, IEEE, Eren S¸ as¸o?glu, Student Member, IEEE, and Rüdiger Urbanke "Polar Codes: Characterization of Exponent, Bounds, and Constructions" IEEE Transactions On Information Theory, Vol. 56, No. 12, December 2010
  6. S. W. Shiv Shankar Mishra, R. K. Nagaria, and S. Tiwari, "New Design Methodologies for High Speed Low Power XOR-XNOR Circuits," World Academy of Science, Engineering and Technology, 2009.
  7. Erdal Ar?kan "Channel Polarization: A Method for Constructing Capacity-Achieving Codes " ISIT 2008, Toronto, Canada, July 6 - 11, 2008
  8. A. B. Shubhajit Roy Chowdhury, Aniruddha Roy, Hiranmay Saha, "A high Speed 8 Transistor Full Adder Design using Novel 3 Transistor XOR Gates," International Journal of Electronics, Circuits and Systems 2;4 2008.
  9. Yibin Ye, Kaushik Roy and Rolf Drechsler "Power Consumption in XOR-Based Circuits",IEEE,0-7803-5012-X/99/@1999.
  10. A. Eslami and H. Pishro-Nik. "On the Performance of Polar Codes under Belief Propagation Decoding", 2010.
Index Terms

Computer Science
Information Sciences


Polar Code XOR-XNOR Gate Power Consumption Power Delay Product (PDP) Delay Power Dissipation.