![]() |
10.5120/15692-4570 |
Karen Thangam Jacob, K.s.ganesh Kumar and B.manjurathi. Article: Selective Compression Technique using Variable-to-Fixed and Fixed-to-Variable Codes. International Journal of Computer Applications 89(13):28-34, March 2014. Full text available. BibTeX
@article{key:article, author = {Karen Thangam Jacob and K.s.ganesh Kumar and B.manjurathi}, title = {Article: Selective Compression Technique using Variable-to-Fixed and Fixed-to-Variable Codes}, journal = {International Journal of Computer Applications}, year = {2014}, volume = {89}, number = {13}, pages = {28-34}, month = {March}, note = {Full text available} }
Abstract
Ìn this paper, we propose two code based techniques: Variable-to-Fixed codes and Fixed-to-Variable codes for power efficient test data compression. The proposed scheme with the aim of achieving high compression ratio and low power consumption relies on reducing, the number of bits for representing the original test vector and the number of transitions per second. Simulation results on ISCAS'89 benchmarks demonstrate that this optimization methodology helps achieve reduced test data volume and power than previous schemes for cases where the number of specified bits in the test set is relatively few.
References
- ZainalabedinNavabi, "Digital System Test and Testable Design,"Springer New York, 2010, pp. 54-61.
- Sankaralingam R. , R. Oruganti and N. A. Touba, "Static compaction techniques to control scan vector power dissipation," in Proceeding IEEE VLSI Test Symp. , 2000, pp. 35-40.
- Hamzaoglu I, Patel JH, "Test set compaction algorithms for combinational circuits," in Proceedings IEEE/ACM international conference on computer-aided design (ICCAD), 1998, pp 283–289.
- Lee J. and N. A. Touba, "LFSR-reseeding scheme achieving low-power dissipation during test," IEEE Trans. Computer-Aided Des. Integr. Circuits Syst. , Vol. 26, No. 2, 2007, pp. 396-401.
- Chandra A. and K. Chakrabarty, "Low-power scan testing and test data compression for system-on-a chip," ,IEEE T. Comput. Aided Design, Vol. 21, 2002, pp. 597-604.
- Chandra A. and K. Chakrabarty, "Combining low power scan testing and test data compression for system-on a chip," Proceeding ACM/IEEE Design Automation Conference, 2001, pp. 166-169.
- Chandra A. and K. Chakrabarty, "Test data compression and test resource partitioning for system-on-a-chip using Frequency-Directed Runlength (FDR) codes," IEEE Trans. Comput. , Vol. 52, No. 8, 2003, pp. 1076-1088.
- Nourani M. , M. Tehranipour and K. Chakabarty, "Nine-coded compression technique with application to reduced pin-count testing and flexible on-chip decompression," In Proceeding Design, Automation, Test in Europe, 2004, pp. 1284-1289.
- El-Maleh AH, "Effcient test compression technique based on block merging," IET ComputDigit Tech, Vol. 2, No. 5, 2008, pp. 327–335.
- Wang, S. and S. K. Gupta, "An automatic test pattern generator for minimizing switching activity during scan testing activity,"IEEE T. Computer-Aided Design Vol. 21, 2002, pp. 954-968.
- Saravanan S. and Har Narayan Upadhyay, "Transition Vector Reduction using Segmentation method based on Compression Technique," Australian Journal of Basic and Applied Sciences, Vol. 5, No. 9, 2012, pp. 2147-2151.
- Saravanan S. and A. Balasubramaniyan, "Run-Length based Compression for selective unspecified test pattern,"Journal of Theoretical and Applied Information Technology, vol. 38, No. 2, 2012
- Rosinger P. M. , et al. , "Analysing trade-offs in scan power and test data compression for systems-on-a-chip," IEEE Proc. Comput. Digital Tech, Vo1. 49, 2002, pp. 188-196.
- Tie-BinWu, Heng-Zhu Liu, Peng-Xia Liu, "Efficient Test Compression Technique for SoC Based on Block Merging and Eight Coding," J Electron Test, Vol. 29, No. 6, 2013, pp. 849-859.
- Nourani M, Tehranipour MH, "RL-Huffman encoding for test compression and power reduction in scan applications," ACM Trans Des Automat Electron Syst, Vol. 10, No. 1, 2005, pp. 91–115.
- Jas A. , J. G. Dastidar, M. E. Ng and N. A. Touba, "An efficient test vector compression scheme using selective Huffman coding," IEEE T. Computer-Aided Des. Integr. Circuits Syst. , Vol. 22, No. 6, 2003, pp. 797-806.
- A. Chandra, and K. Chakrabarty, "A Unified Approach to Reduce SoC Test Data Volume, Scan Power and Testing Time," IEEE Trans. On Computer-Aided Design of Integr. Circuits and systems, Vol. 22, No. 3, 2003, pp. 352-362.