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Reseach Article

Methodology for Power Implementation and Validation at Higher Level of Abstraction

by Amit Kumar Awasthy, Lalita Gupta
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 99 - Number 12
Year of Publication: 2014
Authors: Amit Kumar Awasthy, Lalita Gupta
10.5120/17429-8186

Amit Kumar Awasthy, Lalita Gupta . Methodology for Power Implementation and Validation at Higher Level of Abstraction. International Journal of Computer Applications. 99, 12 ( August 2014), 34-37. DOI=10.5120/17429-8186

@article{ 10.5120/17429-8186,
author = { Amit Kumar Awasthy, Lalita Gupta },
title = { Methodology for Power Implementation and Validation at Higher Level of Abstraction },
journal = { International Journal of Computer Applications },
issue_date = { August 2014 },
volume = { 99 },
number = { 12 },
month = { August },
year = { 2014 },
issn = { 0975-8887 },
pages = { 34-37 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume99/number12/17429-8186/ },
doi = { 10.5120/17429-8186 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:28:04.377718+05:30
%A Amit Kumar Awasthy
%A Lalita Gupta
%T Methodology for Power Implementation and Validation at Higher Level of Abstraction
%J International Journal of Computer Applications
%@ 0975-8887
%V 99
%N 12
%P 34-37
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In earlier generation of IC design technologies the prime parameters of concern were timing and silicon area. The increasing demand for high-performance, battery-operated, system-on-chips in communication and computing has shifted the focus from traditional constraints (such as area, performance, cost, and reliability) to power consumption [1]. In recent years device densities and clock frequency have increased dramatically in devices thereby increasing the power consumption dramatically. During design process the most critical power requirements are tested only after power pins becomes explicit. There are different design strategies for reducing power consumption, and it also becomes critical to make power aware design even if power pins were not explicit or say at very abstraction level of design flow. UPF is used as an IEEE 1801 standard method which provides a consistent way to specifying power implementation intent throughout the design process [2]. Low power validation at very abstraction level uses RTL/Behavioral HDL model along with UPF intent. UPF provide an ability to verify the power intent behavior as early as possible or say at higher abstraction level by overlay the power behavior over the RTL/Behavior HDL model at same abstraction level. This paper describes how HDL model impacted at very higher abstraction level to meet certain power constraints and their validation using an industry accepted IEEE 1801 standard UPF low power validation flow.

References
  1. Version D-2010. 03, March 2010. Synopsys Low-Power Flow User Guide
  2. IEEE Std. 1801™-2009 reference manual, March 2009. IEEE Standard for Design and Verification of Low Power Integrated Circuits
  3. Samir palnitkar, second edition. Verilog HDL: A Guide to Digital Design and Synthesis by Prentice Hall PTR
  4. Kanika Kaur et. al. "Strategies & methodologies for low power vlsi designs: a review" IJAET may 2011 Vol. 1,Issue 2,pp. 159-165
  5. Enrico Macii et. al. "Power modeling, estimation, and optimization", IEEE transactions on computer-aided design of integrated circuits and systems, vol. 17, no. 11, november 1998
  6. J. M. Rabaey and M. Pedram, Eds. , "Low Power Design Methodologies". Norwell, MA: Kluwer Academic, 1996
  7. D. Singh et. al. "Power conscious CAD tools and methodologies: A perspective" Proc. of the IEEE, 83(4): 570-593, 1995.
  8. Mark Horowitz et. al. "Low-Power Digital Design" Center for Integrated Systems, Stanford University, Stanford, CA 94305
Index Terms

Computer Science
Information Sciences

Keywords

HDL (Hardware Description Language) RTL (Register Transfer Level) UPF (Unified Power Format) EDA (Electronic Design Automation) CAD (Computer Aided Design) TCL (Tool Command Language).