CFP last date
22 April 2024
Reseach Article

Power Optimization of 8:1 MUX using Transmission Gate Logic (TGL) with Power Gating Technique

by Abhishek Dixit, Saurabh Khandelwal, Shyam Akashe
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 99 - Number 5
Year of Publication: 2014
Authors: Abhishek Dixit, Saurabh Khandelwal, Shyam Akashe
10.5120/17373-7911

Abhishek Dixit, Saurabh Khandelwal, Shyam Akashe . Power Optimization of 8:1 MUX using Transmission Gate Logic (TGL) with Power Gating Technique. International Journal of Computer Applications. 99, 5 ( August 2014), 37-42. DOI=10.5120/17373-7911

@article{ 10.5120/17373-7911,
author = { Abhishek Dixit, Saurabh Khandelwal, Shyam Akashe },
title = { Power Optimization of 8:1 MUX using Transmission Gate Logic (TGL) with Power Gating Technique },
journal = { International Journal of Computer Applications },
issue_date = { August 2014 },
volume = { 99 },
number = { 5 },
month = { August },
year = { 2014 },
issn = { 0975-8887 },
pages = { 37-42 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume99/number5/17373-7911/ },
doi = { 10.5120/17373-7911 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:27:26.664841+05:30
%A Abhishek Dixit
%A Saurabh Khandelwal
%A Shyam Akashe
%T Power Optimization of 8:1 MUX using Transmission Gate Logic (TGL) with Power Gating Technique
%J International Journal of Computer Applications
%@ 0975-8887
%V 99
%N 5
%P 37-42
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper aims at reducing power and energy dissipation in Transmission Gate Logic (TGL) Multiplexer CMOS circuits comprise of reducing the power supply voltages, power supply current and delay with economical charge recovery logic. This paper designs an 8:1 Multiplexer with CMOS Transmission Gate Logic (TGL) using the Power Gating Technique, which reduces the leakage power and leakage current in active mode. Power Gating Technique uses Transmission Gate Logic (TGL) based an 8:1 multiplexer circuit which removes the degraded output. The PMOS and NMOS transistors are connected together for strong output level. Power gating technique achieves 36% reduction of leakage current and 43% reduction of leakage power in active mode, A the results of this paper are simulated on cadence virtuoso tool realized in 45nm technology with reduction of 4. 021fW power, 7. 381pA current and 0. 7V supply voltage.

References
  1. Ila Gupta, Neha Arora and B. P Singh, "New Design of High Performance 2:1 Multiplexer", International Journal of Engineering Research and Applications (IJERA), vol. 2, no. 2, pp. 1492-1496, Apr 2012.
  2. A. Bellaouar and Mohamed I. Elmasry, "Low-Power Digital VLSI Design: Circuits and Systems", 2nd Edition, pp. 1-530, 1995.
  3. Kang, Sung-Mo, Leblebici and Yusuf, "CMOS Digital Integrated Circuits Analysis and Design", McGraw-Hill International Editions, Boston, 3nd Edition, pp. 1-655, 2003.
  4. Meenakshi Mishra and Shyam Akashe, "High Performance Low Power 200 Gb/s 4:1 MUX with TGL in 45 nm Technology", Journal of Applied Nanoscience, Springer, vol. 4, no. 3, pp 271-277, Feb. 2013.
  5. Paul Metzgen, "A High Performance 32-bit ALU for Programmable Logic", In Proceedings of the 2004 ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, pp. 61–70, 2004
  6. Sarita, Jyoti Hooda, "Design and Implementation of Low Power 4:1 Multiplexer using Adiabatic Logic", International Journal of Innovative Technology and Exploring Engineering (IJITEE), vol. 2, no. 6, pp. 224-228, May 2013.
  7. M. Pedram, "Power minimization in IC design: principles and applications", ACM Transactions on Design Automation of Electronic Systems, vol. 1, no. 1, pp. 3-56, Jan 1996.
  8. S. Anvesh and P. Ramana Reddy, "Optimized Design of an Alu Block Using Power Gating Technique", IOSR Journal of Electronics and Communication Engineering (IOSR-JECE), vol. 4, no. 2, pp. 24-30, Dec 2012.
  9. Saurabh Khandelwal, Shyam Akashe and Sanjay Sharma, "Supply Voltage Minimization Techniques for SRAM Leakage Reduction", Journal of Computational and Theoretical Nanoscience, vol. 9, no. 8, pp. 1044-1048, Aug 2012.
  10. Bhanupriya Bhargava, Pradeep Kumar Sharma and Shyam Akashe "Reduction of Leakage Power using Stacking Power Gating Technique in Different CMOS Design Style at 45Nanometer Regime", International Journal of Computer Applications, vol. 83, no. 1, pp. 19-26, Dec 2013.
  11. Ing-Chao Lin Chin-Hong Lin and Kuan-Hui Li, "Leakage and Aging Optimization Using Transmission Gate-Based Technique", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 1, pp. 87-99, Jan. 2013.
  12. Shiv Shankar Mishra, Adarsh Kumar Agrawal and R. K. Nagaria "A comparative performance analysis of various CMOS design techniques for XOR and XNOR circuits", International Journal on Emerging Technologies, no. 10, pp. 1-10, Feb 2010.
  13. Amreen parveen, Subhasis Bose and Sachin Bandewar " A High Speed Transmission Gate Logic Base 1/N Frequency Divider Digital Parallel Counter Design", International Journal of Engineering and Management Research, vol. 4, no. 3, pp. 132-134, June 2014.
  14. B. Vijayapriya, Dr. S. Padma and Prof. B. M. Prabhu, " Design of Low Power Novel Viterbi Decoder Using Transmission Gates", Int. Journal of Engineering Research and Applications, vol. 3, no. 6, pp. 972-976, Nov-Dec 2013.
  15. N. Seki, L. Zhao, J. Kei, D. Ikebuchi, Y. Kojima, Y. Hasegawa, H. Amano, T. Kashima, S. Takeda, T. Shirai, M. Nakata, K. Usami,T. Sunata, J. Kanai, M. Namiki, M. Kondo, and H. Nakamura, "A fine grain dynamic sleep control scheme in MIPS R3000", In Proc. ICCD, pp. 612–617, Oct 2008.
  16. D. Ikebuchi, N. Seki, Y. Kojima, M. Kamata, L. Zhao, H. Amano, T. Shirai, S. Koyama, T. Hashida, Y. Umahashi, H. Masuda, K. Usami, S. Takeda, H. Nakamura, M. Namiki, and M. Kondo, "Geyser-1: A MIPSR3000 CPU core with fine grain runtime power gating", In Proc. IEEE A-SSCC, pp. 281–284, Nov 2009.
  17. K. Usami and N. Ohkubo, "A design approach for fine-grained run-time power gating using locally extracted sleep signals", In Proc. ICCD, pp. 155–161, Oct 2007.
  18. Swati Mishra and Shyam Akashe, "Diode Based Ground Bounce Noise Reduction for 3-Bit Flash Analog to Digital Converter", International Journal of Advanced Science and Technology, vol. 57, pp. 63-74, August, 2013.
  19. K. Roy, S. Mukhopadhyay and H. Mahmoodi-Meimand, "Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicron CMOS Circuits", In Proceedings of the IEEE, vol. 91, no. 2, pp. 305-327, Feb 2003.
  20. H. Jiao and V. Kursun, "Ground-Bouncing-Noise-Aware Combinational MTCMOS Circuits", In Proceedings IEEE Transactions on Circuits and Systems, vol. 57, no. 8, pp. 2053-2065, Aug 2010.
  21. Toshihide Suzuki, Member, IEEE, Yoichi Kawano, Yasuhiro Nakasha, Shinji Yamaura, Tsuyoshi Takahashi, Kozo Makiyama, and Tatsuya Hirose, "A 50-Gbit/s 450-mW Full-Rate 4:1 Multiplexer With Multiphase Clock Architecture in 0. 13-µm InP HEMT Technology". IEEE Journal of Solid-State Circuits, vol. 42, no. 3, March 2007.
Index Terms

Computer Science
Information Sciences

Keywords

Power Gating Technique Transistor Gate Logic (TGL) Low Power Leakage Circuit