CFP last date
21 October 2024
Reseach Article

FPGA Implementation of Dynamic Energy Efficient Memory Controller for a H.264/AVC Application

Published on None 2011 by A.M. Kulkarni, V. Arunachalam
International Conference and Workshop on Emerging Trends in Technology
Foundation of Computer Science USA
ICWET - Number 12
None 2011
Authors: A.M. Kulkarni, V. Arunachalam
5af783f7-7d23-4c53-9c62-f78cc2b11df2

A.M. Kulkarni, V. Arunachalam . FPGA Implementation of Dynamic Energy Efficient Memory Controller for a H.264/AVC Application. International Conference and Workshop on Emerging Trends in Technology. ICWET, 12 (None 2011), 19-23.

@article{
author = { A.M. Kulkarni, V. Arunachalam },
title = { FPGA Implementation of Dynamic Energy Efficient Memory Controller for a H.264/AVC Application },
journal = { International Conference and Workshop on Emerging Trends in Technology },
issue_date = { None 2011 },
volume = { ICWET },
number = { 12 },
month = { None },
year = { 2011 },
issn = 0975-8887,
pages = { 19-23 },
numpages = 5,
url = { /proceedings/icwet/number12/2155-esa479/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference and Workshop on Emerging Trends in Technology
%A A.M. Kulkarni
%A V. Arunachalam
%T FPGA Implementation of Dynamic Energy Efficient Memory Controller for a H.264/AVC Application
%J International Conference and Workshop on Emerging Trends in Technology
%@ 0975-8887
%V ICWET
%N 12
%P 19-23
%D 2011
%I International Journal of Computer Applications
Abstract

Improvement in high speed DSP applications can be done by integrating computational power with effective memory management. Bandwidth and latency of operation in memory system is rigidly dependent on data accesses. DSP applications such as multimedia require exhaustive streaming at high speed buses. The energy consumption is the key element which will be the focus of research in VLSI and Embedded systems industry. Today a cardinal issue of DSP application is to reduce impact of memory access on execution time while reducing energy consumption of the system. Memory Scheduling is significant in DSP applications to use memory bandwidth effectively. In this paper, we introduce the dynamic memory access scheduling with refresh priority considerations. In addition, a novel bus switching activity monitoring mechanism is implemented to efficaciously reduce the energy consumption of memory operations. H.264/AVC provides higher coding efficiency through added features and functionality, which impose additional computational complexity in encoder and decoder. The features of memory access patterns of H.264 encoder are analyzed. The overhead cycle of page activation has been reduced to improve bus efficiency which also reduces latency of operations. The scheduler and memory controller has been experimented by running a dynamic H.264/AVC application on Xilinx FPGA.

References
  1. Bertrand Le Gal, Emmanuel Casseau, and Sylvain Huet “Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis” IEEE TRANSACTIONS ON VLSI SYSTEMS, VOL. 16, Issue NO. 11, NOVEMBER.2008, pp: 1454-1463.
  2. Hu Hongqi; Sun Jingnan; Xu Jiadong; , "High Efficiency Synchronous DRAM Controller for H.264 HDTV Encoder", 4th IEEE Conference on Industrial Electronics & Applications 2009, pp.2132-2136, 25-27 May 2009.
  3. Ibrahim Hur, CalvinLlin, “Adaptive History-Based Memory Schedulers”, International Symposium on Microarchitecture, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, pp 343 – 354,2004. Jun Shao and Brian T. Davis “A Burst Scheduling Access Reordering Mechanism”, pp: 285-294 Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture.
  4. K.Denolf, C.Blanch, “Initial Memory Complexity Analysis of the AVC CODEC”, SIPS’02, IEEE Workshop.
  5. Memory Systems: Cache, DRAM, Disk. Bruce Jacob, Spencer W. Ng, and David T. Wang, with contributions by Samuel Rodriguez. ISBN 978-0-12-379751-3. Morgan Kaufmann Publishers, September 2007
  6. Ronny Lee Arnold, Donald Charles Soltis, “Preventing Write-After-Write Data Hazards By Cancelling Earlier Write When No Interleaving Instruction Uses Value To Be Written By The Earlier Write”, UNITED STATES PATENT.
  7. Scott Rixner, William J. Dally, Ujval J. Kapasi, Peter Mattson, and John D. Owens “Memory Access Scheduling”, Appears in ISCA-27 (2000)
  8. Shih-Chang Hsia, ‘‘Efficient Memory IP Design for HDTV Coding Application’’, IEEE Trans. Circuits Syst. Video Tech., vol13,June 2003.
  9. Yi-Nung Liu; Meng-Che Chuang; Shao-Yi Chien, "Bandwidth and local memory reduction of video encoders using Bit Plane Partitioning Memory Management“, IEEE International Symposium on Circuits and Systems,2009 (ISCAS 2009). pp.766-769, 24-27 May 2009.
  10. V. Zyuban , P. Kogge “Optimization of high-performance superscalar Power Modes” ,IEEE Transactions on Computers, v.50 n.11, p.1154-1173, November 2001
Index Terms

Computer Science
Information Sciences

Keywords

Multimedia applications Dynamic Memory schedulers Bus switching activity monitoring H.264/AVC