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FPGA Implication of the LUT-SR Family for Uniform Random Number Generation

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IJCA Proceedings on National Conference on Innovative Paradigms in Engineering & Technology 2013
© 2013 by IJCA Journal
NCIPET2013 - Number 7
Year of Publication: 2013
Authors:
M. V. Vyawahare
Rita Rawate

M V Vyawahare and Rita Rawate. Article: FPGA IMPLICATION of the LUT-SR FAMILY for UNIFORM RANDOM NUMBER GENERATION. IJCA Proceedings on National Conference on Innovative Paradigms in Engineering & Technology 2013 NCIPET 2013(7):19-22, December 2013. Full text available. BibTeX

@article{key:article,
	author = {M. V. Vyawahare and Rita Rawate},
	title = {Article: FPGA IMPLICATION of the LUT-SR FAMILY for UNIFORM RANDOM NUMBER GENERATION},
	journal = {IJCA Proceedings on National Conference on Innovative Paradigms in Engineering & Technology 2013},
	year = {2013},
	volume = {NCIPET 2013},
	number = {7},
	pages = {19-22},
	month = {December},
	note = {Full text available}
}

Abstract

Field-programmable gate array (FPGA) optimized random number generators (RNGs) can take advantage of bitwise operations and FPGA-specific features, hence they are more resource-efficient than software-optimized RNGs. This paper describes a type of RNG called a LUT-SR RNG, which takes advantage of bitwise XO R operations and the ability to configure lookup tables (LUTs) into decoders & shift registers of varying lengths. This provides good quality compared to others. The LUT-SR generators is implemented by using VHDL (very high speed integrated circuit hardware description language).

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