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A Comparative Study of Heterogeneous Processor Simulators

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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2016
Authors:
Shagufta, Muhammad Aleem, Muhammad Arshad Islam, Muhammad Azhar Iqbal
10.5120/ijca2016911316

Shagufta, Muhammad Aleem, Muhammad Arshad Islam and Muhammad Azhar Iqbal. A Comparative Study of Heterogeneous Processor Simulators. International Journal of Computer Applications 148(12):5-11, August 2016. BibTeX

@article{10.5120/ijca2016911316,
	author = {Shagufta and Muhammad Aleem and Muhammad Arshad Islam and Muhammad Azhar Iqbal},
	title = {A Comparative Study of Heterogeneous Processor Simulators},
	journal = {International Journal of Computer Applications},
	issue_date = {August 2016},
	volume = {148},
	number = {12},
	month = {Aug},
	year = {2016},
	issn = {0975-8887},
	pages = {5-11},
	numpages = {7},
	url = {http://www.ijcaonline.org/archives/volume148/number12/25807-2016911316},
	doi = {10.5120/ijca2016911316},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

In 1970’s, Gordon Moore perceived that the number of transistors in a processor would double after every 18 months. With the addition of more transistors on a single-chip, a processor’s energy consumption increases exponentially. The solution to this problem is heterogeneous processors and machines. Heterogeneous machine is the combination of CPU and GPU platforms. Computer architecture is shifting from multi-core to heterogeneous era. Generally, computer architects practice of software simulation to model and analyze their ideas. Today, computer architects are using cycle-level simulators to discover and analyze new processor designs. To search the heterogeneous system design-space, we review and practically analyze heterogeneous simulators and their performance. In this study, we present a detailed comparative analysis of gem5-gpu, gem5, and multi2sim simulators.

References

  1. J. Power, J. Hestness, M. S. Orr, M. D. Hill, D. A. Wood, "gem5-gpu: A heterogeneous cpu-gpu simulator," Computer Architecture Letters, vol. 14, no. 1, pp. 34--36, 2015.
  2. N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M. D. Hill, D. A. Wood, "The gem5 simulator," ACM SIGARCH Computer Architecture News, vol. 39, no. 2, pp. 1--7, 2011.
  3. R. Ubal, B. Jang, P. Mistry, D. Schaa, D. Kaeli, "Multi2Sim: a simulation framework for CPU-GPU computing," in ACM, New york, 2012.
  4. J. V. Quiroga Esparza, "Heterogeneous CPU/GPU Memory Hierarchy Analysis and Optimization," Universitat Polit{\`e}cnica de Catalunya, 2015.
  5. Y. Ukidave, "Architectural and Runtime Enhancements for Dynamically Controlled Multi-Level Concurrency on GPUs," Northeastern University Boston, 2015.
  6. P. R. Panda, N. D. Dutt, A. Nicolau, "On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems," ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 5, no. 3, pp. 682--704, 2000.
  7. R. Ubal, J. Sahuquillo, S. Petit and P. Lopez, "Multi2sim: A simulation framework to evaluate multicore-multithread processors," in Citeseer, Rio Grande do Sul , 2007.
  8. R. Ubal, B. Jang, P. Mistry, D. Sachaa, D. Kaeli, "The Multi2Sim Simulation Framework," International Conference on Parallel Architectures and Compilation Techniques, pp. 335--344, 19-23 September 2012.
  9. V. Spiliopoulos, A. Bagdia, A. Hansson, P. Aldworth and S. Kaxiras, "Introducing DVFS-management in a full-system simulator," Modeling, Analysis \& Simulation of Computer and Telecommunication Systems (MASCOTS), 2013 IEEE 21st International Symposium on, pp. 535--545, 14-16 August 2013.
  10. A.Gutierrez, J. Pusdesris, R. Dreslinski, T. Mudge, C. Sudanthi, C. Emmons, and N. Paver, "Sources of error in full-system simulation," Performance Analysis of Systems and Software (ISPASS), 2014 IEEE International Symposium on, pp. 13--22, 23-25 March 2014.
  11. F. A. Endo, D. Couroussé and H. P. Charles, "Micro-architectural simulation of in-order and out-of-order ARM microprocessors with gem5," Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), 2014 International Conference on, pp. 266--273, 14-17 July 2014.
  12. F. A. Endo, D. Couroussé, H.-P. Charles, "Micro-architectural simulation of embedded core heterogeneity with gem5 and McPAT." Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation," Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, p. 17, 22 January 2015.
  13. J. Yin, O. Kayiran, M. Poremba, N. E. Jerger, "Efficient synthetic traffic models for large, complex SoCs," 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 297--308, 12-16 March 2016.
  14. J.-J. Cheng, S.-H. Hung, C.-W. Yeh, "Rapid analysis of interprocessor communications on heterogeneous system architectures via parallel cache emulation," Proceedings of the 2015 Conference on research in adaptive and convergent systems, pp. 418--423, 9-12 October 2015.
  15. H. Wang, V. Sathish, R. Singh, M. J. Schulte, N. S. Kim, "Workload and power budget partitioning for single-chip heterogeneous processors," Proceedings of the 21st international conference on Parallel architectures and compilation techniques, pp. 401--410, 19-23 September 2012.
  16. S. Gurfinkel, "The Distribution of OpenCL Kernel Execution Across Multiple Devices," University of Toronto, Toronto, 2014.
  17. A.Seyhanli, "Memory Controller Design for GPU Simulation in Multi2sim," Universitat Polit`e cnica de Catalunya, Barcelona, 2015.
  18. J. V. Quiroga Esparza, "Heterogeneous CPU/ (GP) GPU Memory Hierarchy Analysis and Optimization," Universitat Polit{\`e}cnica de Catalunya, BarcelonaTech, 2015.
  19. "Multi2Sim," 29 September 2012. [Online]. Available: http://www.multi2sim.org./. [Accessed 21 June 2016].
  20. "Main Page Gem5," 31 May 2011. [Online]. Available: http://www.gem5.org/. [Accessed 21 June 2016].
  21. J. Hestness, S. W. Keckler, D. A. Wood, "A Comparative Analysis of Microarchitecture Effects on CPU and GPU Memory System Behavior," Workload Characterization (IISWC), 2014 IEEE International Symposium on, pp. 150--160, 26-28 October 2014.
  22. P. Petev, "Cache coherence protocol". United State US Patent 11/118,902, 29 April 2005.
  23. J. Power, A. Basu, J. Gu, S. Puthoor, B. M. Bechmann, M. D. Hill, S. K. Reinhardt, D. A. Wood, "Heterogeneous system coherence for integrated CPU-GPU systems", Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 457--467, ACM New York, NY, USA.
  24. A.Munshi, "The OpenCL specification." In 2009 IEEE Hot Chips 21 Symposium (HCS), pp. 1-314. IEEE, 2009.

Keywords

Heterogeneous simulators, gem5-gpu, gem5, multi2sim.