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FPGA Implementation and Analysis of Different Multiplication Algorithm

by Manoj M. Kamble, Sunita P. Ugale
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 149 - Number 2
Year of Publication: 2016
Authors: Manoj M. Kamble, Sunita P. Ugale
10.5120/ijca2016911360

Manoj M. Kamble, Sunita P. Ugale . FPGA Implementation and Analysis of Different Multiplication Algorithm. International Journal of Computer Applications. 149, 2 ( Sep 2016), 33-36. DOI=10.5120/ijca2016911360

@article{ 10.5120/ijca2016911360,
author = { Manoj M. Kamble, Sunita P. Ugale },
title = { FPGA Implementation and Analysis of Different Multiplication Algorithm },
journal = { International Journal of Computer Applications },
issue_date = { Sep 2016 },
volume = { 149 },
number = { 2 },
month = { Sep },
year = { 2016 },
issn = { 0975-8887 },
pages = { 33-36 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume149/number2/25972-2016911360/ },
doi = { 10.5120/ijca2016911360 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:53:40.247064+05:30
%A Manoj M. Kamble
%A Sunita P. Ugale
%T FPGA Implementation and Analysis of Different Multiplication Algorithm
%J International Journal of Computer Applications
%@ 0975-8887
%V 149
%N 2
%P 33-36
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Many of the today’s real time signal processing algorithm included multiplication as its processing heart. In case of signal and image processing, it mostly used functional unit. In this paper we are simulating different multiplication algorithm with their effective architecture. Also paper introducing new multiplication technique using barrel shifter which gives some sort of modification in previously described shift and add multiplication algorithm. Research targeting mainly four algorithms as Vedic vertical crosswise multiplication algorithm, Array multiplier, Shift and add multiplier, Wallace tree multiplier. Further work will carried comparative study of different multiplier with respect to some parameters like logical resources used, delay, power consumption and area. For implementation and parametric analysis, experimental setup uses sparten-3 XC3S400 FPGA as a hardware platform, VHDL coding language for hardware description. Xilinx ISE-simulation tool has many inbuilt compatible facility for parameter analysis like XPE for power analysis. Finally Paper comprises simulation results for 8-bit, 16-bits and 32-bits each of above mentioned multiplier.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Array multiplier Vedic Wallace tree shift and add Barrel shifter.