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FPGA Implementation and Analysis of Different Multiplication Algorithm

by Manoj M. Kamble, Sunita P. Ugale
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 149 - Number 2
Year of Publication: 2016
Authors: Manoj M. Kamble, Sunita P. Ugale

Manoj M. Kamble, Sunita P. Ugale . FPGA Implementation and Analysis of Different Multiplication Algorithm. International Journal of Computer Applications. 149, 2 ( Sep 2016), 33-36. DOI=10.5120/ijca2016911360

@article{ 10.5120/ijca2016911360,
author = { Manoj M. Kamble, Sunita P. Ugale },
title = { FPGA Implementation and Analysis of Different Multiplication Algorithm },
journal = { International Journal of Computer Applications },
issue_date = { Sep 2016 },
volume = { 149 },
number = { 2 },
month = { Sep },
year = { 2016 },
issn = { 0975-8887 },
pages = { 33-36 },
numpages = {9},
url = { },
doi = { 10.5120/ijca2016911360 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
%0 Journal Article
%1 2024-02-06T23:53:40.247064+05:30
%A Manoj M. Kamble
%A Sunita P. Ugale
%T FPGA Implementation and Analysis of Different Multiplication Algorithm
%J International Journal of Computer Applications
%@ 0975-8887
%V 149
%N 2
%P 33-36
%D 2016
%I Foundation of Computer Science (FCS), NY, USA

Many of the today’s real time signal processing algorithm included multiplication as its processing heart. In case of signal and image processing, it mostly used functional unit. In this paper we are simulating different multiplication algorithm with their effective architecture. Also paper introducing new multiplication technique using barrel shifter which gives some sort of modification in previously described shift and add multiplication algorithm. Research targeting mainly four algorithms as Vedic vertical crosswise multiplication algorithm, Array multiplier, Shift and add multiplier, Wallace tree multiplier. Further work will carried comparative study of different multiplier with respect to some parameters like logical resources used, delay, power consumption and area. For implementation and parametric analysis, experimental setup uses sparten-3 XC3S400 FPGA as a hardware platform, VHDL coding language for hardware description. Xilinx ISE-simulation tool has many inbuilt compatible facility for parameter analysis like XPE for power analysis. Finally Paper comprises simulation results for 8-bit, 16-bits and 32-bits each of above mentioned multiplier.

  1. M. Seckora, “Barrel Shifter or Multiply Divide IC Structure,” U.S. Patent 5,465,222, November 1995.
  2. Cem Ergun, seminar at Eastern Mediterranean University on “Multiplication & Division Algorithms”.
  3. P. Saha, A. Banerjee, P. Bhattacharyya, A. Dandapat, 2011 “High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics” IEEE Students' Technology Symposium.
  4. Mrs.Toni J.Billore, Prof.D.R.Rotake May-Jun. 2014 “FPGA implementation of high speed 8 bit Vedic Multiplier using Fast adders” IOSR Journal of VLSI and Signal Processing, PP 54-59.
  5. A. A. Karatsuba: The Complexity of Computations. Proceedings of the Steklov Institute of Mathematics.
  6. H. Bansal, K. G. Sharma, T. Sharma “Wallace Tree Multiplier Designs: A Performance Comparison Review” Innovative Systems Design and Engineering, 2014.
  7. M. Young, the Technical Writer’s Handbook. Mill Valley, CA: University Science, 1989.
  8. S. Vaidya, D. Dandekar “DELAY-POWER PERFORMANCE COMPARISONOF MULTIPLIERS IN VLSI CIRCUIT DESIGN” International Journal of Computer Networks and Communications (IJCNC), Vol.2, No.4, July 2010.
  9. Kripa Mathew, S. Asha Latha, T. Ravi “Design and Analysis of an Array Multiplier Using an Area Efficient Full Adder Cell in 32nm CMOS Technology”, The International Journal of Engineering and Science, volume 2, 2013.
  10. Ch. Harish Kumar, “Implementation and Analysis of Power, Area and Delay of Array, Urdhva, Nikhilam Vedic Multipliers”, International Journal of Scientific and Research Publication, volume-3, January 2013.
  11. Sweta Khatri, Ghanshyam Jangid, “FPGA Impleme-ntation of 64-bit Fast multiplier using barrel shifter”, IJRASET, volume-2, July 2014.
  12. A.Wasil Raseed Ahmed, “FPGA Implementation of Vedic multiplier using VHDL”,
  13. Asmita Haveliya, “FPGA Implementation of Vedic Convolution Algorithm”, IJERA, volume-2, 2012.
  14. Jagdeshwar Rao M and Sanjay Dubey, “A High Speed Wallace Tree Multiplier Using Modified Booth Algorithm for Fast Arithmetic Circuits”, IOSRJECE, volume- 3, Sep. 2012.
  15. B. Dinesh, V. Venkateshwaran, P. Kavinmalar, “Comparison of Regular and Tree based Multiplier Architectures with Modified Booth Encoding for 4-bits on Layout Level using 45nm technology”, IOSR Journal of VLSI and signal processing, May-2014.
Index Terms

Computer Science
Information Sciences


Array multiplier Vedic Wallace tree shift and add Barrel shifter.